eZ80® CPU User Manual

437

TSTIO n

Test I/O Byte

Operation

{0000h, C} AND n

Description

The CPU places the contents of the C register onto the lower byte of the address bus, ADDR[7:0], while it forces the two upper bytes of the address bus, ADDR[23:0], to 0s. The data at this I/O address {0000h, C}, is bitwise ANDed with the 8-bit immediate value n. The appropriate flags are set to 1, depending on the result of the AND logical operation.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Set.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

eZ80® CPU User Manual

438

XOR A, (HL)

Logical Exclusive OR

Operation

A ←A XOR (HL)

Description

The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). This 8-bit value is bitwise exclusive-ORed with the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

eZ80® CPU User Manual

439

XOR A, ir

Logical Exclusive OR

Operation

A ←A XOR ir

Description

The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand is bitwise exclusive-ORed with the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

eZ80® CPU User Manual

440

XOR A, (IX/Y+d)

Logical Exclusive OR

Operation

A ←A XOR (IX/Y+d)

Description

The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-com- plement displacement d. This 8-bit value is bitwise exclusive-ORed with the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

eZ80® CPU User Manual

441

jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 104.

Table 104. Register and jj Op Codes for XOR A, (IX/Y+d) Instruction (hex)

eZ80® CPU User Manual

442

XOR A, n

Logical Exclusive OR

Operation

A ←A XOR n

Description

The 8-bit immediate value n is bitwise exclusive-ORed with the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset.

Attributes

eZ80® CPU User Manual

443

XOR A, r

Logical Exclusive OR

Operation

A ←A XOR r

Description

The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is bitwise exclusive-ORed with the contents of the accumulator, A. The result is written to the accumulator.

Condition Bits Affected

S Set if result is negative; reset otherwise.

Z Set if result is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Reset

Attributes

jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 105.

eZ80® CPU User Manual

444

Table 105. Register and jj Op Codes for XOR A, r Instruction (hex)