eZ80® CPU User Manual
426
STMIX
Set MIXED MEMORY Mode Flag
Operation
MADL ← 1
Description
The MIXED MEMORY Mode Flag (MADL) is set to 1.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
STMIX |
— |
X |
2 |
ED, 7D |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
427
SUB A, (HL)
Subtract without Carry
Operation
A ←A–(HL)
Description
The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). This 8-bit value is subtracted from the contents of the accumulator, A. The result is written to the accumulator.
Condition Bits Affected
S |
Set if result is negative; reset otherwise. |
Z |
Set if result is 0; reset otherwise. |
H |
Set if borrow from bit 4; reset otherwise. |
P/V |
Set if overflow; reset otherwise. |
N |
Set. |
C |
Set if borrow; reset otherwise. |
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
SUB |
A,(HL) |
X |
2 |
96 |
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SUB.S |
A,(HL) |
1 |
3 |
52, 96 |
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SUB.L |
A,(HL) |
0 |
3 |
49, 96 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
428
SUB A, ir
Subtract without Carry
Operation
A ←A–ir
Description
The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand is subtracted from the contents of the accumulator, A. The result is written to the accumulator.
Condition Bits Affected
S |
Set if result is negative; reset otherwise. |
Z |
Set if result is 0; reset otherwise. |
H |
Set if borrow from bit 4; reset otherwise. |
P/V |
Set if overflow; reset otherwise. |
N |
Set. |
C |
Set if borrow; reset otherwise. |
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
SUB |
A,IXH |
X |
2 |
DD, 94 |
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SUB |
A,IXL |
X |
2 |
DD, 95 |
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SUB |
A,IYH |
X |
2 |
FD, |
94 |
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SUB |
A,IYL |
X |
2 |
FD, |
95 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
429
SUB A, (IX/Y+d)
Subtract without Carry
Operation
A ←A–(IX/Y+d)
Description
The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s-com- plement displacement d. This 8-bit value is subtracted from the contents of the accumulator, A. The result is written to the accumulator.
Condition Bits Affected
S |
Set if result is negative; reset otherwise. |
Z |
Set if result is 0; reset otherwise. |
H |
Set if borrow from bit 4; reset otherwise. |
P/V |
Set if overflow; reset otherwise. |
N |
Set. |
C |
Set if borrow; reset otherwise. |
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
SUB |
A,(IX+d) |
X |
4 |
DD, 96, dd |
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SUB.S |
A,(IX+d) |
1 |
5 |
52, DD, 96, dd |
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SUB.L |
A,(IX+d) |
0 |
5 |
49, DD, 96, dd |
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SUB |
A,(IY+d) |
X |
4 |
FD, 96, dd |
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SUB.S |
A,(IY+d) |
1 |
5 |
52, FD, 96, dd |
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SUB.L |
A,(IY+d) |
0 |
5 |
49, FD, 96, dd |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
430
SUB A, n
Subtract without Carry
Operation
A ←A–n
Description
The 8-bit immediate value n is subtracted from the contents of the accumulator, A. The result is written to the accumulator.
Condition Bits Affected
S |
Set if result is negative; reset otherwise. |
Z |
Set if result is 0; reset otherwise. |
H |
Set if borrow from bit 4; reset otherwise. |
P/V |
Set if overflow; reset otherwise. |
N |
Set. |
C |
Set if borrow; reset otherwise. |
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
SUB |
A,n |
X |
2 |
D6, nn |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
431
SUB A, r
Subtract without Carry
Operation
A ←A–r
Description
The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is subtracted from the contents of the accumulator, A. The result is written to the accumulator.
Condition Bits Affected
S |
Set if result is negative; reset otherwise. |
Z |
Set if result is 0; reset otherwise. |
H |
Set if borrow from bit 4; reset otherwise. |
P/V |
Set if overflow; reset otherwise. |
N |
Set. |
C |
Set if borrow; reset otherwise. |
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
SUB |
A,r |
X |
1 |
jj |
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|
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jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 102.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
432
Table 102. Register and jj Op Codes for SUB A, r Instruction (hex)
Register |
jj |
A |
97 |
|
|
B |
90 |
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C |
91 |
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D |
92 |
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E |
93 |
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H |
94 |
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L |
95 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
433
TST A, (HL)
Test
Operation
A AND (HL)
Description
The (HL) operand is an 8-bit value at the memory location specified by the contents of the multibyte register (HL). This 8-bit value is bitwise ANDed with the contents of the accumulator, A. The appropriate flags are set to 1, depending on the result of the AND logical operation. The contents of the accumulator and the memory location are not altered.
Condition Bits Affected
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Set.
P/V Set if parity is even; reset otherwise.
N Reset.
C Reset.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
|
TST |
A,(HL) |
X |
3 |
ED, 34 |
|
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TST.S |
A,(HL) |
1 |
4 |
52, |
ED, 34 |
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TST.L |
A,(HL) |
0 |
4 |
49, |
ED, 73 |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
434
TST A, n
Test
Operation
A AND n
Description
The 8-bit immediate value n is bitwise ANDed with the contents of the accumulator, A. The appropriate flags are set to 1, depending on the result of the AND logical operation. The contents of the accumulator are not altered.
Condition Bits Affected
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Set.
P/V Set if parity is even; reset otherwise.
N Reset.
C Reset
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
TST |
A,n |
X |
3 |
ED, 64, nn |
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UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
435
TST A, r
Test
Operation
A AND r
Description
The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is bitwise ANDed with the contents of the accumulator, A. The appropriate flags are set to 1, depending on the result of the AND logical operation. The contents of the accumulator and the r operand are not altered.
Condition Bits Affected
S Set if result is negative; reset otherwise.
Z Set if result is 0; reset otherwise.
H Set.
P/V Set if parity is even; reset otherwise.
N Reset.
C Reset
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
TST |
A,r |
X |
2 |
ED, jj |
|
|
|
|
|
jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 103.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
436
Table 103. Register and jj Op Codes for TST A, r Instruction (hex)
Register |
jj |
A |
3C |
|
|
B |
04 |
|
|
C |
0C |
|
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D |
14 |
|
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E |
1C |
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H |
24 |
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L |
2C |
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|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |