eZ80® CPU User Manual
338
PUSH AF
Push Stack
Operation
if ADL mode { (SPL–1) ← 00h (SPL–2) ←A (SPL–3) ← F SPL ← SPL–3
}
else Z80 mode { (SPS–1) ←A (SPS–2) ← F SPS ← SPS–2
}
Description
In ADL mode, or when the .L suffix is employed, 3 bytes are pushed onto the memory locations indicated by SPL, in the following sequence:
1.A value of 00h is written to the memory location with address SPL– 1.
2.The CPU writes the contents of the accumulator, A, to the memory location with address SPL–2.
3.The CPU next writes the contents of the Flags Register, F, to the memory location with address SPL–3.
SPL decrements by three.
In Z80 mode, or when the .S suffix is employed, 2 bytes are pushed onto the memory locations indicated by SPS, in the following sequence:
1.The CPU writes the contents of the accumulator, A, to the memory location with address SPS–1.
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
339
2.The CPU next writes the contents of the Flags Register, F, to the memory location with address SPS–2.
SPS decrements by two.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
PUSH |
AF |
0/1 |
3/4 |
F5 |
|
|
|
|
|
PUSH.S |
AF |
1 |
4 |
52, F5 |
|
|
|
|
|
PUSH.L |
AF |
0 |
5 |
49, F5 |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
340
PUSH IX/Y
Push Stack
Operation
if ADL mode {
(SPL–1) ← IX/Y[23:16] (SPL–2) ← IX/Y[15:8] (SPL–3) ← IX/Y[7:0] SPL ← SPL–3
}
else Z80 mode {
(SPS–1) ← IX/Y[15:8] (SPS–2) ← IX/Y[7:0] SPS ← SPS–2
}
Description
In ADL mode, or when the .L suffix is employed, 3 bytes are pushed onto the memory locations indicated by SPL, in the following sequence:
1.The CPU writes the contents of the upper byte of the specified Index Register, IXU or IYU, to the memory location with address SPL–1.
2.The CPU next writes the contents of the High byte of the specified Index Register, IXH or IYH, to the memory location with address SPL–2.
3.The CPU next writes the contents of the Low byte of the specified Index Register, IXL or IYL, to the memory location with address SPL–3.
SPL decrements by three.
In Z80 mode, or when the .S suffix is employed, 2 bytes are pushed onto the memory locations indicated by SPS, in the following sequence:
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
341
1.The CPU writes the contents of the High byte of the specified Index Register, IXH or IYH, to the memory location with address SPS–1.
2.The CPU next writes the contents of the Low byte of the specified Index Register, IXL or IYL, to the memory location with address SPS–2.
SPS decrements by two.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
PUSH |
IX |
0/1 |
4/5 |
DD, E5 |
|
|
|
|
|
PUSH.S |
IX |
1 |
5 |
52, DD, E5 |
|
|
|
|
|
PUSH.L |
IX |
0 |
6 |
49, DD, E5 |
|
|
|
|
|
PUSH |
IY |
0/1 |
4/5 |
FD, E5 |
|
|
|
|
|
PUSH.S |
IY |
1 |
5 |
52, FD, E5 |
|
|
|
|
|
PUSH.L |
IY |
0 |
6 |
49, FD, E5 |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |