eZ80® CPU User Manual

213

INIM

Input from I/O and Increment

Operation

(HL) ← ({UU, 00h, C})

B← B–1

C← C+1 HL ← HL+1

Description

The CPU places the contents of register C onto the lower byte of the address bus, ADDR[7:0], and places a 0 onto the High byte of the address bus, ADDR[15:8]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU reads the byte located at I/O address {UU, 00h, C} into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. The B register decrements. The C and HL registers increment. The Z Flag is set to 1 if the B register decrements to 0.

Condition Bits Affected

eZ80® CPU User Manual

214

Attributes

eZ80® CPU User Manual

215

INIMR

Input from I/O and Increment with Repeat

Operation

repeat {

(HL) ← ({UU, 00h, C})

B← B–1

C← C+1 HL ← HL+1

}while B ≠ 0

Description

The CPU places the contents of register C onto the lower byte of the address bus, ADDR[7:0], and places a 0 onto the High byte of the address bus, ADDR[15:8]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU reads the byte located at I/O address {UU, 00h, C} into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. The B register decrements. The C and HL registers increment. Next, the CPU sets the Z Flag to 1 if the B register decrements to 0. The instruction repeats until the B register equals 0.

Condition Bits Affected

S Not affected.

Z Set if B–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

eZ80® CPU User Manual

216

Attributes