eZ80® CPU User Manual

200

INDM

Input from I/O and Decrement

Operation

(HL) ← ({UU, 00h, C})

B← B–1

C← C–1 HL ← HL–1

Description

The CPU places the contents of register C onto the lower byte of the address bus, ADDR[7:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU reads the byte located at this I/O address into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. Next, the CPU decrements the B, C, and HL registers, and sets the Z Flag to 1 if the B register is decremented to 0.

Condition Bits Affected

eZ80® CPU User Manual

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Attributes

eZ80® CPU User Manual

202

INDMR

Input from I/O and Decrement with Repeat

Operation

repeat {

(HL) ← ({UU, 00h,C})

B← B–1

C← C–1 HL ← HL–1

}while B ≠ 0

Description

The CPU places the contents of register C onto the lower byte of the address bus, ADDR[7:0], and places a 0 onto the High byte of the address bus, ADDR[15:8]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU reads the byte located at I/O address {UU, 00h, C} into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. The CPU decrements the B, C, and HL registers, and sets the Z Flag to 1 if the B register is decremented to 0.

Condition Bits Affected

S Not affected.

Z Set if B–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

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Attributes