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HALT

Halt

Operation

while HALT {

NOP

}

Description

The HALT instruction suspends CPU operation until a subsequent interrupt or reset is received. While in HALT mode, the CPU executes NOPs. The Program Counter, PC, stops incrementing while in HALT mode.

Condition Bits Affected

None.

Attributes

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IM n

Set Interrupt Mode

Operation

Select the appropriate interrupt mode from Interrupt Mode 0, Interrupt

Mode 1, and Interrupt Mode 2.

Description

The n operand is any of the following interrupt modes:

•Interrupt Mode 0—in this mode, the interrupting device inserts an instruction on the data bus during an interrupt acknowledge cycle.

•Interrupt Mode 1—in this mode, the CPU responds to an interrupt by executing a restart to location 000038h.

•Interrupt Mode 2—in this mode, the interrupting device places the low-order address of the interrupt vector on the data bus during an interrupt acknowledge cycle. The I register provides the high-order byte of the interrupt vector table address. The 16-bit value at the address {I, DATA[7:0]} is the starting address of the interrupt service routine.

Condition Bits Affected

None.

Attributes

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Attributes

Not all eZ80® products support the three interrupt modes. Refer to the individual product specification for information on supported interrupt modes.

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IN A, (n)

Input from I/O

Operation

A ← ({UU, A, n})

Description

The n operand is placed on the lower byte of the address bus, ADDR[7:0]; the contents of the accumulator, A, are placed on the middle byte of the address bus, ADDR[15:8]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The byte at I/O address {UU, A, n} is written to the accumulator.

Condition Bits Affected

None.

Attributes

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IN r, (BC)—also IN r, (C) for Z80 compatibility

Input from I/O

Operation

r ← ({UU, BC[15:0]})

Description

The CPU places the contents of the 16-bit BC multibyte register onto the lower two bytes of the address bus at ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The byte located at I/O address {UU, BC[15:0]} is written to the specified register r (A, B, C, D, E, H, or L).

Condition Bits Affected

S Set if byte is negative; reset otherwise.

Z Set if byte is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Not affected.

Attributes

jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 54.

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Table 54. Register and jj Op Codes for IN r, (BC) and IN r, (C) Instructions (hex)

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IN0 r, (n)

Input from I/O

Operation

r ← ({UU, 00h, n})

Description

The n operand is placed on the lower byte of the address bus, ADDR[7:0], while the High byte of the address bus, ADDR[15:8], is forced to 0. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses.The byte at this I/O address is written to the specified register r (A, B, C, D, E, H, or L).

Condition Bits Affected

S Set if byte is negative; reset otherwise.

Z Set if byte is 0; reset otherwise.

H Reset.

P/V Set if parity is even; reset otherwise.

N Reset.

C Not affected.

Attributes

jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 55

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Table 55. Register and jj Op Codes for IN0 r, (n) Instruction (hex)

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INC (HL)

Increment

Operation

(HL) ← (HL)+1

Description

The (HL) operand is an 8-bit value stored at the memory location specified by the contents of the multibyte register HL. This 8-bit value increments by 1.

Condition Bits Affected

Attributes

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INC ir

Increment

Operation

ir ← ir+1

Description

The ir operand is any of the 8-bit CPU registers IXH, IXL, IYH, IYL. The contents of the specified register increment by 1.

Condition Bits Affected

Attributes

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INC IX/Y

Increment

Operation

IX/Y ← IX/Y+1

Description

The CPU increments the contents of the specified Index Register, IX or IY, by 1. In Z80 mode, or when the .S suffix is employed, IX/Y[23:16] ←

00h.

Condition Bits Affected

None.

Attributes

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INC (IX/Y+d)

Increment

Operation

(IX/Y+d) ← (IX/Y+d)+1

Description

The (IX/Y+d) operand is an 8-bit register at the memory location specified by the contents of the Index Register, IX or IY, added to the two’s- complement displacement d. The CPU increments the contents of this 8- bit register by 1.

Condition Bits Affected

Attributes

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INC r

Increment

Operation

r ← r+1

Description

The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU increments the contents of the specified register r by 1.

Condition Bits Affected

Attributes

jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the Op Codes indicated in Table 56.

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Table 56. Register and jj Op Codes for INC r Instruction (hex)

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INC rr

Increment

Operation

rr ← rr+1

Description

The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU increments the contents of the specified register by 1. In Z80 mode, or when the .S suffix is employed, rr[23:16] ← 00h.

Condition Bits Affected

None.

Attributes

kk identifies the BC, DE, or HL register and is assembled into one of the Op Codes indicated in Table 57.

Table 57. Register and kk Op Codes for INC rr Instruction (hex)

Register kk

BC 03

DE 13

HL 23

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INC SP

Increment

Operation

SP ← SP+1

Description

The CPU increments the contents of the Stack Pointer register (SP) by 1. In ADL mode, or when the .L suffix is employed, SPL is used for SP. In Z80 mode, or when the .S suffix is employed, SPS is used for SP.

Condition Bits Affected

None.

Attributes

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IND

Input from I/O and Decrement

Operation

(HL) ← ({UU, BC[15:0]}) B ← B–1

HL ← HL–1

Description

The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU reads the byte located at this I/O address into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. Next, the CPU decrements the B and HL registers and sets the Z Flag to 1 if the B register is decremented to 0.

Condition Bits Affected

S Not affected.

Z Set if B-1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

Attributes

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IND2

Input from I/O and Decrement

Operation

(HL) ← ({UU, BC[15:0]})

B← B–1

C← C–1 HL ← HL–1

Description

The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus, ADDR[15:0]. The upper byte of the address bus, ADDR[23:16], is undefined for I/O addresses. The CPU reads the byte located at this I/O address into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. Next, the CPU decrements the B, C, and HL registers, and sets the Z Flag to 1 if the B register is decremented to 0.

Condition Bits Affected

S Not affected.

Z Set if B–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

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Attributes

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IND2R

Input from I/O and Decrement with Repeat

Operation

repeat {

(HL) ← ({UU, DE[15:0]}) BC ← BC–1

DE ← DE–1

HL ← HL–1 } while BC ≠ 0

Description

The CPU places the contents of DE[15:0] onto the lower two bytes of the address bus, ADDR[15:0]. The upper byte of the address bus, ADDR[23:16], is undefined for I/O addresses. The CPU reads the byte at this I/O address into CPU memory. The CPU next places the contents of HL onto the address bus and writes the byte to the memory address specified by the HL register. Next, the CPU decrements the BC, DE, and HL registers, and sets the Z Flag to 1 if the BC register is decremented to 0. The instruction repeats until the BC register equals 0.

Condition Bits Affected

S Not affected.

Z Set if BC–1=0; reset otherwise.

H Not affected.

P/V Not affected.

N Set if msb of data is a logical 1; reset otherwise.

C Not affected.

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Attributes

Note

This instruction operates differently in the eZ80190 devicedevice. In the eZ80190, operation is:

repeat {

(HL) ← ({UU, BC[15:0]})

B← B–1

C← C–1 HL ← HL–1

}while B ≠ 0