eZ80® CPU User Manual
172
DJNZ d
Decrement B Jump not 0
Operation
B ← B–1 if B ≠ 0 {
PC ← PC+d
}
Description
The B register decrements by 1. If the resultant value in register B is not 0, the two’s-complement displacement d is added to the value of the Program Counter. The jump is measured from the address of the instruction Op Code following this instruction.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
DJNZ |
d |
X |
2/4 |
10, dd |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
173
EI
Enable Interrupt
Operation
IEF1 ← 1
IEF2 ← 1
Description
This instruction sets the interrupt enable flags (IEF1 and IEF2) to a logical 1, which allows any maskable interrupt to be recognized.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
EI |
— |
X |
1 |
FB |
|
|
|
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|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
174
EX AF, AF’
Exchange AF and AF’
Operation
A ↔A’
F ↔ F’
Description
The CPU exchanges the contents of the accumulator, A, and the Flag register, F, with the contents of the alternate accumulator, A’, and alternate Flag register, F’, respectively.
Condition Bits Affected
All condition bits are replaced with the values from the alternate Flag register, F’.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
EX |
AF,AF’ |
X |
1 |
08 |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
175
EX DE, HL
Exchange DE with HL
Operation
DE ↔ HL
Description
The CPU exchanges the contents of the DE register with the contents of the HL register.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
EX |
DE,HL |
X |
1 |
EB |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
176
EX (SP), HL
Exchange Stack and HL Register
Operation
if ADL = 1 {
(SPL) ↔ HL[7:0] (SPL+1) ↔ HL[15:8] (SPL+2) ↔ HL[23:16]
}
else if ADL = 0 { SPS ↔ HL[7:0]
(SPS+1) ↔ HL[15:8]
}
Description
The CPU exchanges the contents of the multibyte CPU register HL with the contents of the memory location specified by the Stack Pointer (SP). In ADL mode, or when the .L suffix is employed, SPL is used for SP. In Z80 mode, or when the .S suffix is employed, SPS is used for SP.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
EX |
(SP),HL |
0/1 |
5/7 |
E3 |
|
|
|
|
|
EX.S |
(SP),HL |
1 |
6 |
52, E3 |
|
|
|
|
|
EX.L |
(SP),HL |
0 |
8 |
49, E3 |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
177
EX (SP), IX/Y
Exchange Stack and Index Register
Operation
if ADL=1 {
(SPL) ↔ IX/Y[7:0] (SPL+1) ↔ IX/Y[15:8] (SPL+2) ↔ IX/Y[23:16]
}
else if ADL=0 { SPS ↔ IX/Y[7:0]
(SPS+1) ↔ IX/Y[15:8]
}
Description
The CPU exchanges the contents of the multibyte Index Register, IX or IY, with the memory location specified by the Stack Pointer (SP). In ADL mode, or when the .L suffix is employed, SPL is used for SP. In Z80 mode, or when the .S suffix is employed, SPS is used for SP.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
EX |
(SP),IX |
0/1 |
6/8 |
DD, E3 |
|
|
|
|
|
EX.S |
(SP),IX |
1 |
7 |
52, DD, E3 |
|
|
|
|
|
EX.L |
(SP),IX |
0 |
9 |
49, DD, E3 |
|
|
|
|
|
EX |
(SP),IY |
0/1 |
6/8 |
FD, E3 |
|
|
|
|
|
EX.S |
(SP),IY |
1 |
7 |
52, FD, E3 |
|
|
|
|
|
EX.L |
(SP),IY |
0 |
9 |
49, FD, E3 |
|
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|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |
eZ80® CPU User Manual
178
EXX
Exchange Working Register Set with Alternate Register Set
Operation
BC ↔ BC’
DE ↔ DE’
HL ↔ HL’
Description
The CPU exchanges the contents of the primary working registers BC, DE, and HL with the alternate working registers BC’, DE’, and HL’, respectively.
Condition Bits Affected
None.
Attributes
Mnemonic |
Operand |
ADL Mode |
Cycle |
Op Code (hex) |
EXX |
— |
X |
1 |
D9 |
|
|
|
|
|
UM007712-0503 |
PRELIMINARY |
CPU Instruction Set |