In general, the MSRs have no usefulness to application or operating system software and are not used. (This is to be expected since the MSRs are different on each processor.) Appendix A contains a detailed description of the VIA Eden ESP’s MSRs.

3.4 OMITTED FUNCTIONS

This section summarizes those functions that are not in the VIA Eden ESP processor.

Symmetric Multiprocessing Support: APIC

This bus function is omitted since the target market for the VIA Eden ESP processor is small form factor PC’s, internet appliances, and fanless PC’s.

A bit in the feature identification returned from the CPUID instruction indicates whether this feature is present or not. This enhancement is not provided on the VIA Eden ESP processor.

Other Functions

There are other functions that are not implemented in the VIA Eden ESP processor. These are identified accordingly in the CPUID feature flags, Conditional Move instructions, Page Attribute Tables, 4-Mbyte pages, 36-bit Page Size Extension, and FXSAVE/FXRSTOR instructions.

The VIA Eden ESP processor contains a 64KB L2 cache. Model specific registers pertaining to the L2 cache are detailed in Appendix A. Model specific registers pertaining to APIC, Machine Check, and Debug and Trace features are not supported.