
- •Preface
- •About this document
- •Further reading
- •Feedback
- •Introduction
- •1.1 About the ARM PrimeCell Static Memory Controller (PL092)
- •Functional Overview
- •2.1 ARM PrimeCell SMC overview
- •2.2 PrimeCell SMC operation
- •2.3 Memory shadowing
- •2.4 Test interface controller operation
- •2.5 Data bus interface operation
- •2.6 Using the SMC with an external bus multiplexer or SDRAM controller
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 PrimeCell SMC registers
- •Programmer’s Model for Test
- •4.1 Scan testing
- •A.1 AMBA AHB interface signals
- •A.2 AMBA AHB slave interface signals
- •A.3 AMBA AHB master interface signals
- •A.4 Internal signals
- •A.5 Input/output pad signals

Chapter 4
Programmer’s Model for Test
This chapter describes the registers of the ARM PrimeCell Static Memory Controller (PL092) and provides details required when programming the microcontroller. It contains the following:
•Scan testing on page 4-2.
ARM DDI 0203B |
Copyright © ARM Limited 2001. All rights reserved. |
4-1 |

Programmer’s Model for Test
4.1Scan testing
The PrimeCell SMC has been designed to simplify:
•the insertion of scan test cells
•the use of Automatic Test Pattern Generation (ATPG).
This is the recommended method of manufacturing test.
4-2 |
Copyright © ARM Limited 2001. All rights reserved. |
ARM DDI 0203B |

Appendix A
ARM PrimeCell Static Memory Controller
(PL092) Signal Descriptions
This chapter describes the AMBA AHB and module-specific non-AMBA AHB signals used with the ARM PrimeCell SMC. It contains the following sections:
•AMBA AHB interface signals on page A-2
•AMBA AHB slave interface signals on page A-3
•AMBA AHB master interface signals on page A-5
•Internal signals on page A-7
•Input/output pad signals on page A-9.
ARM DDI 0203B |
Copyright © ARM Limited 2001. All rights reserved. |
A-1 |

ARM PrimeCell Static Memory Controller (PL092) Signal Descriptions
A.1 AMBA AHB interface signals
Table A-1 describes the common AMBA AHB signals.
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Table A-1 Common AMBA AHB signals |
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Signal name |
Type |
Source/ |
Description |
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destination |
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nHCLK |
Input |
Clock control |
Inverted bus clock input. It is used |
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only for the generation of the write |
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enable output. |
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HCLK |
Input |
Clock control |
Bus clock input, that times all bus |
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transfers. All signal timings are |
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related to the rising edge. |
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HRESETn |
Input |
Reset controller |
Bus reset input, active LOW, used to |
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reset the system and the bus when |
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asserted LOW. |
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HREADYIN |
Input |
Other AHB slaves |
Transfer completed input. When |
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HIGH the HREADYIN signal |
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indicates that a transfer has finished |
on the bus. This signal can be driven LOW to extend a transfer.
A-2 |
Copyright © ARM Limited 2001. All rights reserved. |
ARM DDI 0203B |