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ARM PrimeCell static memory controller technical reference manual.pdf
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Chapter 4

Programmer’s Model for Test

This chapter describes the registers of the ARM PrimeCell Static Memory Controller (PL092) and provides details required when programming the microcontroller. It contains the following:

Scan testing on page 4-2.

ARM DDI 0203B

Copyright © ARM Limited 2001. All rights reserved.

4-1

Programmer’s Model for Test

4.1Scan testing

The PrimeCell SMC has been designed to simplify:

the insertion of scan test cells

the use of Automatic Test Pattern Generation (ATPG).

This is the recommended method of manufacturing test.

4-2

Copyright © ARM Limited 2001. All rights reserved.

ARM DDI 0203B

Appendix A

ARM PrimeCell Static Memory Controller

(PL092) Signal Descriptions

This chapter describes the AMBA AHB and module-specific non-AMBA AHB signals used with the ARM PrimeCell SMC. It contains the following sections:

AMBA AHB interface signals on page A-2

AMBA AHB slave interface signals on page A-3

AMBA AHB master interface signals on page A-5

Internal signals on page A-7

Input/output pad signals on page A-9.

ARM DDI 0203B

Copyright © ARM Limited 2001. All rights reserved.

A-1

ARM PrimeCell Static Memory Controller (PL092) Signal Descriptions

A.1 AMBA AHB interface signals

Table A-1 describes the common AMBA AHB signals.

 

 

Table A-1 Common AMBA AHB signals

 

 

 

 

Signal name

Type

Source/

Description

destination

 

 

 

 

 

 

 

nHCLK

Input

Clock control

Inverted bus clock input. It is used

 

 

 

only for the generation of the write

 

 

 

enable output.

 

 

 

 

HCLK

Input

Clock control

Bus clock input, that times all bus

 

 

 

transfers. All signal timings are

 

 

 

related to the rising edge.

 

 

 

 

HRESETn

Input

Reset controller

Bus reset input, active LOW, used to

 

 

 

reset the system and the bus when

 

 

 

asserted LOW.

 

 

 

 

HREADYIN

Input

Other AHB slaves

Transfer completed input. When

 

 

 

HIGH the HREADYIN signal

 

 

 

indicates that a transfer has finished

on the bus. This signal can be driven LOW to extend a transfer.

A-2

Copyright © ARM Limited 2001. All rights reserved.

ARM DDI 0203B