- •Preface
- •About this document
- •Intended audience
- •Organization
- •Typographical conventions
- •Timing diagram conventions
- •Further reading
- •ARM publications
- •Other publications
- •Feedback
- •Feedback on this document
- •Feedback on the ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050)
- •1 Introduction
- •1.1 About the ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050)
- •1.1.1 Features of the PrimeCell KMI
- •1.2 AMBA compatibility
- •2 Functional Overview
- •2.1 ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) overview
- •2.2 PrimeCell KMI functional description
- •2.2.1 AMBA APB interface and register block
- •2.2.2 Transmit block
- •2.2.3 Receive block
- •2.2.4 Controller block
- •2.2.5 Timer/clock divider blocks
- •2.2.6 Synchronization logic
- •2.2.7 Test registers and logic
- •2.3 PrimeCell KMI operation
- •2.3.1 Interface reset
- •2.3.2 Clock signals
- •2.3.3 Keyboard clock and data signals
- •2.3.4 Keyboard/mouse data output
- •2.3.5 Keyboard data input
- •2.3.6 Timing requirements
- •3 Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Summary of PrimeCell KMI registers
- •3.3 Register descriptions
- •3.3.1 KMICR: [6] (+ 0x00)
- •3.3.3 KMIDATA: [8] (+ 0x08)
- •3.3.4 KMICLKDIV: [4] (+ 0x0C)
- •3.3.5 KMIIR: [2] (+ 0x10)
- •3.4 Interrupts
- •3.4.1 Interrupt generation logic
- •4 Programmer’s Model for Test
- •4.1 PrimeCell KMI test harness overview
- •4.2 Scan testing
- •4.3 Test registers
- •4.3.2 KMITCR [5] (+0x80)
- •4.3.3 KMITMR [4] (+0x84)
- •4.3.4 KMITISR [2] (+0x88)
- •4.3.5 KMITOCR [3] (+0x8c)
- •4.3.6 KMISTG1 [6] (+0x90)
- •4.3.7 KMISTG2 [5] (+0x94)
- •4.3.8 KMISTG3 [8] (+0x98)
- •4.3.9 KMISTATE [4] (+0x9c)
- •A.1 AMBA APB signals
- •A.2 On-chip signals
- •A.3 Signals to pads
Chapter 2
Functional Overview
This chapter describes the major functional blocks of the ARM PrimeCell PS2
Keyboard/Mouse Interface (PL050) and contains the following sections:
•ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) overview on page 2-2
•PrimeCell KMI functional description on page 2-3
•PrimeCell KMI operation on page 2-6.
DDI 0143C |
© Copyright ARM Limited 1999. All rights reserved. |
2-1 |
Functional Overview
2.1ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) overview
The ARM PrimeCell KMI provides a keyboard or mouse interface that is IBM PS2 or AT-compatible. The interface uses clock and data lines to implement a half-duplex bidirectional synchronous serial interface.
The PrimeCell KMI performs serial-to-parallel conversion on the data received from the keyboard/mouse peripheral, and parallel-to-serial conversion on the data transmitted to the peripheral. The CPU reads and writes data and control/status information via the AMBA APB interface.
In a typical configuration, KMIDATAIN and KMICLKIN inputs are connected to bidirectional input/output pads which have pull-up resistors for the pins KMIDATA and KMICLK. The outputs are high-impedance by default until the active LOW tristate enables nKMIDATAEN or nKMICLKEN are asserted LOW to pull the output pins LOW.
A reference clock KMIREFCLK is required to generate an internal 8MHz signal and a 4-bit divide allows division of the clock by 1 to 16.
After reset, the interface can be enabled to wait for one of two events:
•If data is written to the transmit register, a transmit sequence is initiated and the data is transmitted serially from the PrimeCell KMI.
•If the clock signal is pulled LOW by the keyboard/mouse peripheral, a receive sequence begins and data is clocked into the PrimeCell KMI.
The PrimeCell KMI can generate two individual maskable interrupts. These indicate one of the following situations:
•the transmit buffer is empty and another byte can be transmitted
•a byte has been received from the keyboard/mouse peripheral.
2-2 |
© Copyright ARM Limited 1999. All rights reserved. |
DDI 0143C |
