List of Figures

Key to timing diagram conventions ............................................................................

xvi

Figure 2-1

PrimeCell MPMC block diagram ...............................................................................

2-2

Figure 2-2

Pad interface block diagram ......................................................................................

2-8

Figure 2-3

TIC block diagram .....................................................................................................

2-9

Figure 2-4

PrimeCell MPMC in an example system .................................................................

2-10

Figure 3-1

Peripheral identification register bit assignment ......................................................

3-36

Figure 5-1

External memory zero wait state read timing diagram ..............................................

5-8

Figure 5-2

External memory two wait state read timing diagram ................................................

5-9

Figure 5-3

External memory two output enable delay state read timing diagram .....................

5-10

Figure 5-4

External memory two zero wait state reads timing diagram ....................................

5-11

Figure 5-5

External memory zero wait fixed length burst read timing diagram .........................

5-12

Figure 5-6

External memory two wait states fixed length burst read timing diagram ...............

5-13

Figure 5-7

External memory page mode read transfer timing diagram ....................................

5-14

Figure 5-8

External memory 32-bit burst read from 8-bit memory timing diagram ...................

5-15

Figure 5-9

External memory zero wait state write timing diagram ............................................

5-16

Figure 5-10

External memory two wait state write timing diagram .............................................

5-17

Figure 5-11

External memory two write enable delay state write timing diagram .......................

5-18

Figure 5-12

External memory two zero wait writes timing diagram ............................................

5-19

Figure 5-13

Read followed by write (both zero wait) with no turnaround ....................................

5-20

Figure 5-14

Write followed by read (both zero wait) with no turnaround ....................................

5-21

Figure 5-15

Read followed by a write (all zero wait state) with two turnaround cycles ...............

5-22

ARM DDI 0215A

Copyright © 2002 ARM Limited. All rights reserved.

xi

Figure 5-16

Memory banks constructed from 8-bit memory ......................................................

5-24

Figure 5-17

Memory banks constructed from 16-bit memory ....................................................

5-24

Figure 5-18

Memory bank constructed from 32-bit memory ......................................................

5-25

Figure 5-19

Typical memory connection diagram ......................................................................

5-26

Figure 7-1

A write transfer to a write protected chip select ........................................................

7-3

Figure 7-2

An SDRAM auto-refresh cycle ..................................................................................

7-3

Figure 7-3

An INCR, INCR4, or WRAP4 burst read transfer, buffer hit .....................................

7-5

Figure 7-4

Three sequential reads, burst type SINGLE, read transfer, buffer hit .......................

7-6

Figure 7-5

Three nonsequential reads, burst type SINGLE, read transfer, buffer hit .................

7-7

Figure 7-6

An INCR8 or WRAP8 burst read transfer, buffer hit .................................................

7-8

Figure 7-7

Two simultaneous INCR, INCR4, or WRAP4 burst read transfer, buffer hit .............

7-9

Figure 7-8

Four word INCR, INCR4, or WRAP4 burst write ....................................................

7-10

Figure 7-9

Three sequential write transfers .............................................................................

7-11

Figure 7-10

Three nonsequential write transfers .......................................................................

7-12

Figure 7-11

INCR8 or WRAP8 burst write .................................................................................

7-13

Figure 7-12

Two simultaneous INCR, INCR4, or WRAP4 burst write transfer, buffer hit ..........

7-14

Figure 9-1

MPMC system interconnection diagram ...................................................................

9-3

Figure 9-2

PMU self-refresh .....................................................................................................

.. 9-6

Figure 9-3

PMU self-refresh waveforms ....................................................................................

9-7

Figure 9-4

Forcing AHB masters idle in a multi-layer system ....................................................

9-9

Figure 9-5

Example system .....................................................................................................

9-10

Figure 10-1

Clock feed back ....................................................................................................

10-19

Figure 10-2

x8 SDRAM device .................................................................................................

10-22

Figure 10-3

x16 SDRAM connection ........................................................................................

10-23

Figure 10-4

x32 SDRAM interconnection .................................................................................

10-24

Figure 10-5

Mixed width SDRAM memory devices ..................................................................

10-25

Figure 10-6

SRAM and SDRAM memory devices ...................................................................

10-27

Figure 10-7

Medium performance systems ..............................................................................

10-28

Figure 10-8

Lower performance systems .................................................................................

10-29

Figure A-1

On-chip to off-chip delay for a single signal ..............................................................

A-3

Figure A-2

On-chip to off-chip delay with skew for a single signal .............................................

A-5

Figure A-3

On-chip to off-chip delay with skew for multiple signals ...........................................

A-5

Figure A-4

SDRAM timing diagram ............................................................................................

A-8

Figure A-5

Memory controller to SDRAM memory timing path ..................................................

A-9

Figure A-6

SDRAM memory to memory controller timing path ................................................

A-10

xii

Copyright © 2002 ARM Limited. All rights reserved.

ARM DDI 0215A