Functional Overview

2.4Timing requirements

The clock output is routed back to the PrimeCell MMCI and is used to clock the output registers, to meet the hold time requirements of MMCICMD and MMCIDAT. Figure 2-14 shows a block diagram of the clock output routing.

Figure 2-14 Clock output retiming logic

Functional Overview

Ensure that you meet the input and timing requirements when integrating the PrimeCell MMCI in a system. Figure 2-15 shows the signal relationship.

MCLK

MMCICLK

Feedback clock delay

Figure 2-15 MMCICMD and MMCIDAT timing