Programmer’s Model for Test
4.3.6ACITCDR_L [8] (+0x90)
ACITCDR is the test clock divider register, LOW byte. This is a read-only register that provides observation for the bottom 8 bits of the clock divide counter values during test. The counter is a 10-bit, free-running counter that decrements in intervals of two.
Table 4-7 shows the bit assignments for the ACITCDR_L.
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Table 4-7 ACITCDR_L register |
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Bit |
Name |
Description |
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7:0 |
ACICDCNT_L |
A read of this register returns the current count of the clock |
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divide counter, bits 7-0. |
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4.3.7ACITCDR_H [2] (+0x94)
ACITCDR_H is the test clock divider register, HIGH byte. This is a read-only register that provides observation for the top 2 bits of the clock divide counter values during test. Table 4-8 shows the bit assignments for the ACI TCDR_H.
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Table 4-8 ACITCDCR_H register |
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Bit |
Name |
Description |
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7:2 |
- |
Reserved, read unpredictable. |
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1:0 |
ACICDCNT_H |
A read of this register returns the current count of the clock |
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divide counter, bits 9-8. |
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4-8 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0146C |
Appendix A
ARM PrimeCell Audio CODEC Interface(PL040)
Signal Descriptions
This appendix describes the signals that interface with the ARM PrimeCell Audio
CODEC Interface (PL040). It contains the following sections:
•AMBA APB signals on page A-2
•On-chip signals on page A-3
•Signals to pads on page A-4.
ARM DDI 0146C |
© Copyright ARM Limited 1999. All rights reserved. |
A-1 |
ARM PrimeCell Audio CODEC Interface (PL040) Signal Descriptions
A.1 AMBA APB signals
The PrimeCell ACI module is connected to the AMBA APB as a bus slave. With the exception of the BnRES signal, the AMBA APB signals have a P prefix and are active HIGH. Active LOW signals contain a lower case n. The AMBA APB signals are described in Table A-1.
Table A-1 AMBA APB signal descriptions
Name |
Type |
Source/ |
Description |
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destination |
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BnRES |
Input |
Reset controller |
Bus reset signal, active LOW. |
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PADDR[7:2] |
Input |
APB bridge |
Subset of AMBA APB address bus. |
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PCLK |
Input |
Clock generator |
AMBA APB clock, used to time all bus |
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transfers. |
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PENABLE |
Input |
APB bridge |
AMBA APB enable signal. PENABLE |
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is asserted HIGH for one cycle of PCLK |
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to enable a bus transfer cycle. |
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PRDATA [7:0] |
Output |
APB bridge |
Subset of unidirectional AMBA APB |
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read data bus |
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PSEL |
Input |
APB bridge |
PrimeCell ACI select signal from |
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decoder. When set to 1 this signal |
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indicates that the slave device is selected |
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by the AMBA APB bridge, and that a |
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data transfer is required. |
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PWDATA [7:0] |
Input |
APB bridge |
Subset of unidirectional AMBA APB |
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write data bus. |
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PWRITE |
Input |
APB bridge |
AMBA APB transfer direction signal, |
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indicates a write access when HIGH, |
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read access when LOW. |
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A-2 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0146C |
ARM PrimeCell Audio CODEC Interface (PL040) Signal
A.2 On-chip signals
A free-running reference clock, ACICLK, must be provided. By default it is assumed to be asynchronous to PCLK. Synchronizing registers are used for signals crossing between PCLK and ACICLK domains.
If PCLK and ACICLK are always synchronous then the HDL could be modified to remove the synchronizing registers, but this will also necessitate modification of the test vectors. The on-chip signals required in addition to the APB signals are shown in Table A-2.
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Table A-2 On-chip signals |
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Name |
Type |
Source/ |
Description |
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destination |
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ACICLK |
Input |
Clock generator |
PrimeCell ACI clock. |
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nACIRST |
Input |
Reset controller |
PrimeCell ACI reset signal to ACICLK clock domain, active LOW. |
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The reset controller must use BnRES to assert nACIRST |
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asynchronously, but negate it synchronously with ACICLK. |
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ACITXINTR |
Output |
Interrupt controller |
Transmit interrupt request. Active HIGH interrupt request asserted |
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whenever the transmit FIFO is at least half empty. |
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ACIRXINTR |
Output |
Interrupt controller |
Receive interrupt request. Active HIGH interrupt request asserted |
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whenever the receive FIFO is at least half full. |
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ACIINTR |
Output |
Interrupt controller |
PrimeCell ACI interrupt request, active HIGH. A single combined |
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interrupt generated as an OR function of the two individual maskable |
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interrupts above. |
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SCANMODE |
Input |
Test controller |
Scan test hold input. When scan test is used, this signal must be |
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asserted HIGH during scan testing to ensure that internal data storage |
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elements can be asynchronously reset. |
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SCANMODE must be negated LOW during normal use or when |
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applying manufacturing test vectors via the Test Interface controller |
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(TIC). |
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The reset inputs should be asynchronously asserted but synchronously negated for each of the clock domains within the ACI. This ensures that logic is reset even if clocks are not present, to avoid any static power consumption problems at power up.
The interrupt functionality is described in Interrupts on page 3-8.
ARM DDI 0146C |
© Copyright ARM Limited 1999. All rights reserved. |
A-3 |