Programmer’s Model for Test
4.3Test registers
The PrimeCell ACI test registers are memory-mapped as shown in Table 4-1.
Table 4-1 Test registers memory map
Address |
Type |
Width |
Reset value |
Name |
Description |
|
|
|
|
|
|
ACI Base + 0x40–0x7c |
Read/write |
0 |
- |
ACITCER |
Test clock enable register. |
|
|
|
|
|
|
ACI Base + 0x80 |
Read/write |
5 |
b---00000 |
ACITCR |
Test control register. |
|
|
|
|
|
|
ACI Base + 0x84 |
Read/write |
3 |
b-----000 |
ACITMR |
Test mode register. |
|
|
|
|
|
|
ACI Base + 0x88 |
Read/write |
1 |
b-------0 |
ACITISR |
Test input stimulus register. |
|
|
|
|
|
|
ACI Base + 0x8c |
Read |
4 |
b----0000 |
ACITOCR |
Test output capture register. |
|
|
|
|
|
|
ACI Base + 0x90 |
Read |
8 |
b00000000 |
ACITCDR_L Test clock divider register, |
|
|
|
|
|
|
LOW byte. |
|
|
|
|
|
|
ACI Base + 0x94 |
Read |
2 |
b------00 |
ACITCDR_H Test clock divider register, |
|
|
|
|
|
|
HIGH byte. |
|
|
|
|
|
|
Each register shown in Table 4-1 is described below.
4.3.1ACITCER [0] (+0x40–0x7c)
ACITCER is the test clock enable register. This is a 0-bit register. Table 4-2 shows the bit assignments for the ACITCER.
|
|
Table 4-2 ACITCER register |
|
|
|
Bit |
Name |
Description |
|
|
|
7:0 |
- |
When in registered clock mode (refer to ACITCR [5] (+0x80) on |
|
|
page 4-5), a test clock enable is produced only when this register is |
|
|
accessed (read or write). The clock enable pulse is HIGH for one period of |
|
|
PCLK. |
|
|
|
ACITCER has a multiple word space in the register address map to allow for the generation of multiple test clock enable pulses.
Note
ACICLK must be driven by PCLK during test.
4-4 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0146C |
Programmer’s Model for Test
4.3.2ACITCR [5] (+0x80)
ACITCR is the test control register. This general test register controls operation of the PrimeCell ACI under test conditions. Table 4-3 shows the bit assignments for the ACITCR.
|
|
Table 4-3 ACITCR register |
|
|
|
Bit |
Name |
Description |
|
|
|
7:5 |
- |
Reserved, read unpredictable, should be written as 0. |
|
|
|
4 |
Test Input Select |
By default, this bit is cleared to 0 for normal operation. This |
|
(TESTINPSEL) |
bit selects the source for the internal input signal for external |
|
|
non-AMBA inputs. |
|
|
When this bit is cleared to 0, the primary inputs are taken |
|
|
from the external pads (normal operation). |
|
|
When this bit is set to 1, the values programmed in ACITISR |
|
|
are used to drive the internal line. |
|
|
|
3 |
Test Reset |
By default, this bit is cleared to 0 for normal operation when |
|
(TESTRST) |
reset by BnRES. |
|
|
When this bit is set to 1, a reset is asserted throughout the |
|
|
module, EXCEPT for the test registers (this simulates reset by |
|
|
BnRES being asserted to 0). |
|
|
|
2 |
Registered Clock |
This bit selects the internal test clock mode: |
|
Mode (REGCLK) |
0 = Strobe clock mode is selected which generates a test clock |
|
|
enable on every APB access (read or write) to the block. Use |
|
|
of strobe clock mode allows testing with less test vectors |
|
|
when testing functions such as counters. The Test Clock |
|
|
Enable is generated from PENABLE ANDed with PSEL. |
|
|
1 = Registered clock mode is selected which only generates a |
|
|
test clock enable on an APB access to the ACITCER (ACI |
|
|
test clock enable register) location. |
|
|
This bit has no effect unless bit 0 and bit 1 are both set to 1. |
|
|
This bit is cleared to 0 by default on reset by BnRES. |
|
|
|
1 |
Test Clock Enable |
This bit selects the source of the test clock: |
|
(TESTCLKEN) |
0 = The internal clock enable is continuously HIGH. |
|
|
1 = The internal test clock enable is selected, so that the test |
clocks are enabled for only one period of the input clock per APB access. The internal clock enable mode depends on the setting of bit 2.
This bit has no effect unless bit 0 is set to 1.
This bit is cleared to 0 by default on reset by BnRES.
ARM DDI 0146C |
© Copyright ARM Limited 1999. All rights reserved. |
4-5 |
Programmer’s Model for Test
|
|
|
Table 4-3 ACITCR register (continued) |
|
|
|
|
Bit |
Name |
Description |
|
|
|
|
|
0 |
Test Mode Enable |
0 |
= Normal operating mode is selected. |
|
(TESTEN) |
1 |
= Test mode is selected. |
Bits 1 and 2 have no effect unless bit 0 is set to 1.
This bit is cleared to 0 by default on reset by BnRES.
4.3.3ACITMR [3] (+0x84)
ACITMR is the test mode register and controls the specific test modes for the PrimeCell ACI. These test modes improve controllability so that a high fault coverage can be achieved. All the bits are read as 0 after reset. Table 4-4 shows the bit assignments for the ACITMR.
|
|
Table 4-4 ACITMR register |
|
|
|
Bit |
Name |
Description |
|
|
|
7:3 |
- |
Reserved, read unpredictable, should be written as 0. |
|
|
|
2 |
ACI Upper Bit |
When TESTCOUNT = 1 and DECUPPER = 1 then the clock |
|
Decrement |
divider counter upper bit is decremented on each clock enable |
|
(DECUPPER) |
(read ACITCDR bit 9). |
|
|
This bit is cleared to 0 by default on reset by BnRES. |
|
|
|
1 |
ACI Nibble |
When TESTCOUNT = 1 and DECNIBBLE = 1 then both |
|
Decrement |
clock divider counter nibbles are decremented on each clock |
|
(DECNIBBLE) |
enable (read ACITCDR bits 8-5 and 4-1). |
|
|
This bit is cleared to 0 by default on reset by BnRES. |
|
|
|
0 |
ACI Clock Divider |
Setting this bit to 1 enables the clock divider nibble test |
|
Test Count Enable |
mode. This test mode enables verification of counter |
|
(TESTCOUNT) |
functionality in less clock enable cycles and decrements are |
|
|
controlled by DECNIBBLE and DECUPPER bits in this |
|
|
register. |
For normal operation clear to 0 so that the counter decrements by 1 on each clock cycle.
This bit is cleared to 0 by default on reset by BnRES.
Note
The test registers must not be accessed during normal operation.
4-6 |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0146C |
Programmer’s Model for Test
4.3.4ACITISR [1] (+0x88)
ACITISR is the test input stimulus register and provides test mode stimulus for the ACIDATAIN input to the PrimeCell ACI. When the TESTINPSEL bit in the ACITCR register is 1, the value in the ACIDATAIN bit in the ACITISR register is routed to the internal ACIDATAIN line. Table 4-5 shows the bit assignments for the ACITISR.
|
|
Table 4-5 ACITISR register |
|
|
|
Bit |
Name |
Description |
|
|
|
7:1 |
- |
Reserved, read unpredictable, should be written as 0. |
|
|
|
0 |
TESTDATAIN |
Test data input for the ACIDATAIN pin. |
|
|
|
4.3.5ACITOCR [4] (+0x8c)
ACITOCR is the test output capture register and is a read-only register that provides observability for the primary outputs of the PrimeCell ACI. The ACIINTR interrupt is an OR of the three individual interrupts ACIRXINTR, ACITXINTR and ACIRORINTR. Table 4-6 shows the bit assignments for the ACITOCR.
|
|
Table 4-6 ACITOCR register |
|
|
|
Bit |
Name |
Description |
|
|
|
7:4 |
- |
Reserved, read unpredictable. |
|
|
|
3 |
ACIINTR |
Test observation for primary output ACIINTR. |
|
|
|
2 |
ACIBITCLK |
Test observation for primary output ACIBITCLK. |
|
|
|
1 |
ACIFSYNC |
Test observation for primary output ACIFSYNC. |
|
|
|
0 |
ACIDATAOUT |
Test observation for primary output ACIDATAOUT. |
|
|
|
ARM DDI 0146C |
© Copyright ARM Limited 1999. All rights reserved. |
4-7 |