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Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

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Электротехника

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ARM PrimeCell advanced audio codec interface technical reference manual.pdf

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Chapter 3

Programmer’s Model

This chapter describes the ARM PrimeCell AACI (PL041) registers and provides details needed when programming the microcontroller. It contains the following sections:

•About the programmer’s model on page 3-2

•Summary of PrimeCell AACI registers on page 3-3

•Register descriptions on page 3-7

•Interrupts on page 3-36

•System loopback testing on page 3-40

•Software restrictions on page 3-41

•Frequency restriction on page 3-44.

ARM DDI 0173B

3-1

Programmer’s Model

3.1About the programmer’s model

The base address of the PrimeCell AACI is not fixed, and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.

The following locations are reserved and must not be used during normal operation:

•locations at offsets 0x110-0x17F and 0x190-0xFDC are reserved for possible future extensions.

3-2

ARM DDI 0173B

Programmer’s Model

3.2Summary of PrimeCell AACI registers

The PrimeCell AACI registers are shown in Table 3-1.

Table 3-1 PrimeCell AACI register summary

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

AACI base + 0x00	Read/write	29	0x00000000	AACIRXCR1	Control register
					for receive FIFO1.

AACI base + 0x04	Read/write	17	0x00000	AACITXCR1	Control register
					for transmit
					FIFO1.

AACI base + 0x08	Read	12	0x00B	AACISR1	Status register
					channel 1.

AACI base + 0x0C	Read	7	0x00	AACIISR1	Interrupt status
					channel 1.

AACI base + 0x10	Read/write	7	0x00	AACIIE1	Interrupt enable
					channel 1.

AACI base + 0x14	Read/write	29	0x00000000	AACIRXCR2	Control register
					for receive FIFO2.

AACI base + 0x18	Read/write	17	0x00000	AACITXCR2	Control register
					for transmit
					FIFO2.

AACI base + 0x1C	Read	12	0x00B	AACISR2	Status register
					channel 2.

AACI base + 0x20	Read	7	0x00	AACIISR2	Interrupt status
					channel 2.

AACI base + 0x24	Read/write	7	0x00	AACIIE2	Interrupt enable
					channel 2.

AACI base + 0x28	Read/write	29	0x00000000	AACIRXCR3	Control register
					for receive FIFO3.

AACI base + 0x2C	Read/write	17	0x00000	AACITXCR3	Control register
					for transmit
					FIFO3.

AACI base + 0x30	Read	12	0x00B	AACISR3	Status register
					channel 3.

ARM DDI 0173B

3-3

Programmer’s Model

Table 3-1 PrimeCell AACI register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

AACI base + 0x34	Read	7	0x00	AACIISR3	Interrupt status
					channel 3.

AACI base + 0x38	Read/write	7	0x00	AACIIE3	Interrupt enable
					channel 3.

AACI base + 0x3C	Read/write	29	0x00000000	AACIRXCR4	Control register
					for receive FIFO4.

AACI base + 0x40	Read/write	17	0x00000	AACITXCR4	Control register
					for transmit
					FIFO4

AACI base + 0x44	Read	12	0x00B	AACISR4	Status register
					channel 4.

AACI base + 0x48	Read	7	0x00	AACIISR4	Interrupt status
					channel 4.

AACI base + 0x4C	Read/write	7	0x00	AACIIE4	Interrupt enable
					channel 4.

AACI base + 0x50	Read	20	0x00000	AACISL1RX	Data received on
					slot 1.

AACI base + 0x54	Read/write	20	0x00000	AACISL1TX	Data transmitted
					on slot 1.

AACI base + 0x58	Read	20	0x00000	AACISL2RX	Data received on
					slot 2.

AACI base + 0x5C	Read/write	20	0x00000	AACISL2TX	Data transmitted
					on slot 2.

AACI base + 0x60	Read	20	0x00000	AACISL12RX	Data received on
					slot 12.

AACI base + 0x64	Read/write	20	0x00000	AACISL12TX	Data transmitted
					on slot 12.

AACI base + 0x68	Read/write	14	0x0A80	AACISLFR	Slot flag register

AACI base + 0x6C	Read	8	0x00	AACISLISTAT	Slot interrupt
					status register.

3-4

ARM DDI 0173B

Programmer’s Model

Table 3-1 PrimeCell AACI register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

AACI base + 0x70	Read/write	9	0x000	AACISLIEN	Slot interrupt
					enable register.

AACI base + 0x74	Write	13	-	AACIINTCLR	Interrupt clear
					register.

AACI base + 0x78	Read/write	12	0x000	AACIMAINCR	Main control
					register.

AACI base + 0x7C	Read/write	1	0x1	AACIRESET	RESET control
					register.

AACI base + 0x80	Read/write	1	0x0	AACISYNC	SYNC control
					register.

AACI base + 0x84	Read	28	0x0000000	AACIALLINTS	All FIFO interrupt
					status register.

AACI base + 0x88	Read	2	0x0	AACIMAINFR	Main flag register.

AACI base + 0x90-0xAC	Read/write	32	0x00000000	AACIDR1	Data read or
					written, from or to
					FIFO1.

AACI base + 0xB0-0xCC	Read/write	32	0x00000000	AACIDR2	Data read or
					written, from or to
					FIFO2.

AACI base + 0xD0-0xEC	Read/write	32	0x00000000	AACIDR3	Data read or
					written, from or to
					FIFO3.

AACI base + 0xF0-Ox10C	Read/write	32	0x00000000	AACIDR4	Data read or
					written, from or to
					FIFO4.

AACI base + 0x110-Ox17F	-	-	-	-	Reserved.

AACI base + 0x180-Ox18C	-	-	-	-	Reserved for test
					purposes.

AACI base + 0x190-OxFDC	-	-	-	-	Reserved.

AACI base + 0xFE0	Read	8	0x41	AACIPERIPHID0	Identification
					register, bits 7:0.

ARM DDI 0173B

3-5

Programmer’s Model

Table 3-1 PrimeCell AACI register summary (continued)

Address	Type	Width	Reset	Name	Description
Address	Type	Width	value	Name	Description
			value

AACI base + 0xFE4	Read	8	0x10	AACIPERIPHID1	Identification
					register, bits 15:8.

AACI base + 0xFE8	Read	8	0x04	AACIPERIPHID2	Identification
					register, bits
					23:16.

AACI base + 0xFEC	Read	8	0x00	AACIPERIPHID3	Identification
					register bits,
					31:24.

AACI base + 0xFF0	Read	8	0x0D	AACIPCELLID0	PrimeCell
					identification
					register, bits 7:0.

AACI base + 0xFF4	Read	8	0xF0	AACIPCELLID1	PrimeCell
					identification
					register, bits 15:8.

AACI base + 0xFF8	Read	8	0x05	AACIPCELLID2	PrimeCell
					identification
					register, bits
					23:16.

AACI base + 0xFFC	Read	8	0xB1	AACIPCELLID3	PrimeCell
					identification
					register, bits
					31:24.

Data to or from the FIFOs can be read, or written to eight sequential addresses. This allows the microprocessor to use its load and store multiple operands to read or write to the FIFO.

3-6

ARM DDI 0173B

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