
- •Preface
- •About this document
- •Further reading
- •Feedback
- •Introduction
- •1.1 About the ARM PrimeCell AACI (PL041)
- •Functional Overview
- •2.1 ARM PrimeCell AACI (PL041) overview
- •2.3 PrimeCell AACI functional description
- •2.4 PrimeCell AACI operation
- •2.5 DMA interface bus protocol
- •Programmer’s Model
- •3.1 About the programmer’s model
- •3.2 Summary of PrimeCell AACI registers
- •3.3 Register descriptions
- •3.4 Interrupts
- •3.5 System loopback testing
- •3.6 Software restrictions
- •3.7 Frequency restriction
- •Programmer’s Model for Test
- •4.1 PrimeCell AACI test harness overview
- •4.2 Scan testing
- •4.3 Test registers
- •4.4 Integration testing of block inputs
- •4.5 Integration testing of block outputs
- •4.6 Integration test summary
- •A.1 AMBA APB signals
- •A.2 Module-specific signals
- •Frame format
- •B.1 AACISDATAOUT frame format
- •B.2 AACISDATAIN frame format

Chapter 1
Introduction
This chapter describes the ARM PrimeCell Advanced Audio CODEC Interface (PL041). It contains the following section:
•About the ARM PrimeCell AACI (PL041) on page 1-2.
ARM DDI 0173B |
Copyright © ARM Limited 2000. All rights reserved. |
1-1 |

Introduction
1.1About the ARM PrimeCell AACI (PL041)
The ARM PrimeCell Advanced Audio CODEC Interface (AACI) is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB). The PrimeCell AACI provides communication to off-chip CODECs that support the AC-link protocol.
Examples of these CODECs include:
•the WM9704Q from Wolfson Microelectronics Ltd
•the CS4299 from Cirrus Logic
•and the LM4549 from National Semiconductor Corporation.
AC97 CODECs offer a route for high-quality audio, modem support, and provision for headsets.
1.1.1Features of the PrimeCell AACI
The PrimeCell AACI has the following features:
•Four channels are available and can be in operation simultaneously. This allows support for four different sample rates simultaneously.
•The channels can be serviced either by Direct Memory Access (DMA) or by the processor.
•Each channel has transmit and receive FIFOs.
•The four channels allow independence between modem, audio, headset and microphone channels.
1-2 |
Copyright © ARM Limited 2000. All rights reserved. |
ARM DDI 0173B |

Introduction
Figure 1-1 is a simplified block diagram of a PrimeCell AACI.
PRESETn |
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PWDATA[31:0] |
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AACIRESET |
PRDATA[31:0] |
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PADDR[11:2] |
APB |
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interface |
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Timing |
AACIBITCLK |
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PWRITE |
and |
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controller |
AACISYNC |
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register |
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PSEL |
block |
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PENABLE |
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PCLK |
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Receive |
Frame |
Receive |
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FIFO |
shift |
AACISDATAIN |
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decoder |
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channel |
register |
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Interrupts |
Interrupts |
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and |
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FIFO |
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level status |
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Transmit |
Frame |
Transmit |
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generator |
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FIFO |
shift |
AACISDATAOUT |
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and slot 0 |
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channel |
register |
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generator |
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Figure 1-1 Simplified block diagram of a PrimeCell AACI showing one channel
ARM DDI 0173B |
Copyright © ARM Limited 2000. All rights reserved. |
1-3 |

Introduction
1-4 |
Copyright © ARM Limited 2000. All rights reserved. |
ARM DDI 0173B |