Programmer’s Model for Test
4.6Integration test summary
Table 4-6 summarizes the integration test strategy for all PrimeCell AACI pins.
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Table 4-6 PrimeCell AACI integration test strategy |
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Name |
Type |
Source/ |
Test strategy |
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destination |
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PCLK |
In |
APB |
Register read/write. |
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PRESETn |
In |
APB |
Register read/write. |
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PADDR[11:2] |
In |
APB |
Register read/write. |
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PWDATA[31:0] |
In |
APB |
Register read/write. |
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PRDATA[31:0] |
Out |
APB |
Register read/write. |
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PENABLE |
In |
APB |
Register read/write. |
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PWRITE |
In |
APB |
Register read/write. |
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PSEL |
In |
APB |
Register read/write. |
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AACIBITCLK |
In |
Primary |
Indirectly tested by performing a data transfer. |
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nAACIBITCLK |
In |
Clock |
Not tested using integration test vectors. |
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generator |
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AACISDATAOUT |
Out |
Primary |
Use integration vector trickbox, and AACIITIP, |
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AACIRESET, AACISYNC, and AACIITOP registers. |
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AACISDATAIN |
In |
Primary |
Use integration vector trickbox, and AACIITIP, |
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AACIRESET, AACISYNC, and AACIITOP registers. |
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SCANENABLE |
In |
Test controller |
Not tested using integration test vectors. |
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SCANINPCLK |
In |
Test controller |
Not tested using integration test vectors. |
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SCANINnBITCLK |
In |
Test controller |
Not tested using integration test vectors. |
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SCANINBITCLK |
In |
Test controller |
Not tested using integration test vectors. |
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SCANOUTPCLK |
Out |
Test controller |
Not tested using integration test vectors. |
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SCANOUTBITCLK |
Out |
Test controller |
Not tested using integration test vectors. |
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SCANOUTnBITCLK |
Out |
Test controller |
Not tested using integration test vectors. |
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AACIINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
4-18 |
Copyright © ARM Limited 2000. All rights reserved. |
ARM DDI 0173B |
Programmer’s Model for Test
Table 4-6 PrimeCell AACI integration test strategy (continued)
Name |
Type |
Source/ |
Test strategy |
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destination |
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AACIRXINTR1 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIRXINTR2 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIRXINTR3 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIRXINTR4 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACITXINTR1 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACITXINTR2 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACITXINTR3 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACITXINTR4 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIRXTOINTR1 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIRXTOINTR2 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIRXTOINTR3 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIRXTOINTR4 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACITXCINTR1 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACITXCINTR2 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACITXCINTR3 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACITXCINTR4 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIURINTR1 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIURINTR2 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIURINTR3 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIURINTR4 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIORINTR1 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIORINTR2 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIORINTR3 |
Out |
Intra-chip |
Use AACIITOP0 register. |
ARM DDI 0173B |
Copyright © ARM Limited 2000. All rights reserved. |
4-19 |
Programmer’s Model for Test
Table 4-6 PrimeCell AACI integration test strategy (continued)
Name |
Type |
Source/ |
Test strategy |
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destination |
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AACIORINTR4 |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIWINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIGPIOINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIS1RXINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIS1TXINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIS2RXINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIS2TXINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIS12RXINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIS12TXINTR |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIDMASREQRX |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIDMALSREQRX |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIDMABREQRX |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIDMALBREQRX |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIDMACLRRX |
In |
Intra-chip |
Use AACIITIP register. |
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AACIDMABREQTX |
Out |
Intra-chip |
Use AACIITOP0 register. |
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AACIDMACLRTX |
In |
Intra-chip |
Use AACIITIP register. |
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AACISYNC |
Out |
Primary |
Use integration vector trickbox, AACITIP, AACITOP, |
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AACISYNC and AACIRESET registers. |
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AACIRESET |
Out |
Primary |
Use integration vector trickbox, AACITIP, AACITOP, |
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AACISYNC and AACIRESET registers. |
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AACIRXTOFEINTR1 |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIRXTOFEINTR2 |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIRXTOFEINTR3 |
Out |
Intra-chip |
Use AACIITOP1 register. |
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AACIRXTOFEINTR4 |
Out |
Intra-chip |
Use AACIITOP1 register. |
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4-20 |
Copyright © ARM Limited 2000. All rights reserved. |
ARM DDI 0173B |
Programmer’s Model for Test
Note
nAACIBITCLKRST and nFAACIBITCLKRST are implicity tested through integration methodology. At least one reset value test will fail if nAACIBITCLKRST and nFAACIBITCLKRST are not applied properly.
ARM DDI 0173B |
Copyright © ARM Limited 2000. All rights reserved. |
4-21 |
Programmer’s Model for Test
4-22 |
Copyright © ARM Limited 2000. All rights reserved. |
ARM DDI 0173B |
Appendix A
ARM PrimeCell AACI (PL041) Signal
Descriptions
This appendix describes the signals which interface with the PrimeCell Advanced Audio CODEC Interface (PL041) block. It contains the following:
•AMBA APB signals on page A-2
•Module-specific signals on page A-3.
ARM DDI 0173B |
Copyright © ARM Limited 2000. All rights reserved. |
A-1 |