- •Preface
- •1. RF CMOS Transceivers
- •2. CMOS Short Range Wireless Transceivers
- •3. Wireless Transmission Protocols
- •4. CMOS PAs: Related Design Issues
- •5. CMOS PAs: Recent Progress
- •6. Motivation
- •7. Outline
- •1. Introduction
- •2. Conjugate Match and Load line Match
- •3. Effect of the Transistor Knee Voltage
- •4. Classification of Power Amplifiers
- •4.1 Class A, B, AB, and C PAs
- •4.2 Class E
- •4.3 Class F
- •5. Power Amplifier Linearization
- •5.1 Feed Forward
- •5.2 Doherty Amplifier
- •5.3 Envelope Elimination and restoration
- •5.4 Linear Amplification Using Nonlinear Components
- •6. Spectral Regrowth
- •7. Power Amplifier Stability Issues
- •8. Power Amplifier Controllability
- •9. Summary
- •1. Introduction
- •2. Class E PA Circuit Design
- •2.1 Driver Stage Design
- •2.2 Simulated Performance
- •3. Effect of Finite Ground inductance
- •4. Layout Considerations
- •5. Testing Procedures and Results
- •7. Summary
- •1. Introduction
- •2. CMOS Power Amplifier Design
- •2.1 Design of the Output Stage
- •2.2 Driver Stage
- •2.3 Power Control Implementation
- •3. Implementation and Simulation Results
- •4. Experimental Results
- •5. Summary
- •1. A CMOS PA for Class 2/3 Bluetooth
- •3. Simulations Results
- •3.1 Large Signal Simulations
- •3.2 Power Control
- •3.3 Gain and Matching
- •3.4 Stability
- •4. Conclusion
- •5. Summary
82 RF CMOS POWER AMPLIFIERS:THEORY,DES1GN AND IMPLEMENTATION
3.2Power Control
The output power can be controlled through the variation in the bias voltage applied to the cascode transistor in the output stage. It is worth noting that since the supply voltage in the output stage is higher than that of the first driver stage, controlling the gain of the driver stage can not bring the output power to low levels since the gain of the second stage is much higher. In order to have a wide range of output power variation, the biasing of the cascode transistor can be changed, thus changing the loading on the main amplifier, and therefore changes the output power, and efficiency. In order to achieve specific control steps, a Digital to Analog Converter (DAC) has to feed the cascode bias pin. Figure 5.15 shows the variation in output power, and efficiency versus the cascode voltage bias. Using the same technique of varying the width of the main amplifier in the output stage as discussed in section 4.2, has shown many sta- bility issues compared to this technique.
