3
Bus Hardware and Signals
Understanding the data and address buses is critical, because they are at the heart of interfacing design. This chapter will discuss what a bus is, how data are put onto it, and how data from it is used. The chapter progresses logically, with the first section covering basic concepts in digital hardware, the next section using those concepts to describe the control signals on the bus, and the final section discussing the important issue of timing in the microprocessor bus.
The first section of this chapter is a condensed version of background material on computer realization (as opposed to architecture, organization, and software discussed in earlier chapters) needed to understand the remainder of the book. This led to the study of bus timing and control - very important to the design of interfaces. Its importance can be shown in the following experience. Microcomputer manufacturers have applications engineers who write notes on how to use the chips the companies manufacture and who answer those knotty questions that systems designers can't handle. The author had an opportunity to sit down with Charlie Melear, one of the very fine applications engineers at Motorola's plant, when the first edition of this book was written. Charlie noted that the two most common problems designers have are (1) improper control signals for the bus, whereby several bus drivers are given commands to drive the bus at the same time, and (2) failure to meet timing specifications for address and data buses. These problems, which will be covered in §3.2.2, remain. Even today, when much of the hardware is on a single chip and the designer isn't concerned about them, they reappear when I/O and memory chips are added to a single-chip microcontroller.
This chapter introduces a lot of terminology to provide background for later sections and enable you to read data sheets provided by the manufacturers. The terminology is close to that used in industry, and microprocessor notation conforms to that used in Motorola data sheets. However, some minor deviations have been introduced where constructs appear so often in this book that further notation is useful.
This chapter should provide enough background in computer organization for the remaining sections. After reading the chapter, you should be able to read a logic diagram or the data sheets describing microcomputers or their associated integrated circuits, and you also should have a fundamental knowledge of the signals and their timing on a typical microcomputer bus.
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3.1 Digital Hardware |
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variable means make it false; and complement a variable means make it true if it was false or make it false if it was true. Two possible relations exist between signals and variables. In positive logic, a high signal represents a true variable and a low signal, a false variable. In negative logic, a high signal represents a false variable and a low signal, a true variable. Signals, which can be viewed on an oscilloscope or a logic analyzer, are preferred when someone, especially a technician, deals with actual hardware. Variables have a more conceptual significance and seem to be preferred by designers, especially in the early stages of design, and by programmers, especially when writing I/O software. Simply put, "true" and "false" are the 1 and 0 of the programmer, the architect, and the system designer; and "high" and "low" are the 1 and 0 of the technician and1C manufacturer. While nothing is wrong with using 1 and 0 where the meaning is clear, we use the words "true" and "false" when talking about software or system design and the words "high" and "low" when discussing the hardware realization, to be clear.
Two types of variables and their corresponding signals are important in hardware, A memory variable is capable of being made true or false and of retaining this value, but a link variable is true or false as a result of functions of other variables. A link variable is always some function of other variables (as the output of some gate). At a high level of abstraction, these variables operate in different dimensions; memory variables are used to convey information through time (at the same point in space), while link variables convey information through space (at the same point in time). Some transformationson hardware, like converting from a parallel to a serial adder, are nicely explained by this abstract view. For instance, one can convert a parallel adder into a serial adder by converting a link variable that passes the carry into a memory variable that saves the carry. Also, in a simulation program, we differentiate between the types because memory variables have to be initialized and link variables don't.
A synchronous signal is associated with a periodic variable (for example, a square wave) called a clock. The signal or variable is indeterminate except when the clock is asserted. Or, alternatively, the value of the signal is irrelevant except when the clock is asserted. Depending on the context, the signal is determinate either precisely when the clock changes from false to true or as long as the clock is true. The context depends on what picks up the signal and will be discussed when we study the flip-flop. This is so in the real world because of delays resulting from circuitry, noise, and transmission-line ringing. In our abstraction of the signal, we simply ignore the signal except when this clock is asserted, and we design the system so the clock is asserted only when we can guarantee the signal is determinate under worst-case conditions. Though there are asynchronous signals where there is no associated clock and the signals are supposed to be determinate at all times, most microprocessor signals are synchronous; thus in further discussions, we will assume all signals are synchronous. Then two signals are equivalent if they have the same (H or L) value whenever the clock is asserted.
The other basic idea is that of the module, which is a block of hardware with identifiable input, output, and memory variables. Input variables are the input ports and output variables are the output ports. Often, we are interested only in the behavior. Modules are hehaviorally equivalent if, for equivalent values of the initial memory variables and equivalent sequences of values of input variables, they deliver equivalent sequences of values of output variables. Thus, we are concerned not about how they are constructed internally, what the precise voltages are, or what the signals are when the clock is not asserted, but only about what the signals are when the clock is asserted.
3.2 Address and Control Signals in 6812 Microcontrollers
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Timing diagrams are used to show the requirements. A timing diagram is like an oscilloscope trace of the signals, as is shown in Figure 3.5. For collections of variables, like the 16 address lines shown by the trace labeled A, two parallel lines indicate that any particular address line may be high or low but will remain there for the time interval where the lines are parallel. A crossing line indicates that any particular line can change at that time. A line in the middle of the high and low line levels indicates the output is floating because no drivers are enabled, or the output may be changing as it tries to reach a stable value. A line in the middle means the signal is indeterminate; it is not necessarily at half the voltage. (Motorola also uses a Crosshatch pattern like a row of Xs to indicate that the signal is invalid but not Instated, while a line in the middle means the output is in the tristate open circuit mode on the device being discussed. That distinction is not made in this book, because both cases mean that the bus signal is indeterminate and cannot be used.) Timing is usually shown to scale, as on an oscilloscope, and requirements are indicated the way dimensions are shown on a blue print. On the left, the "dimension arrow" shows that addresses change 50 nanoseconds after C rises, and,in the middle, the "dimension arrow" shows that the address should be stable for at least 150 nanoseconds.
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Address and Control Signals in 6812 Microcontrollers |
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changes in this interval, the microprocessor may randomly input either an L or H on that line. The memory is responsible for providing valid and constant signals during this interval during the setup and hold time. In a write cycle, the R/W signal is guaranteed low at the time the address becomes stable and can rise 25 nanoseconds after the beginning of the next cycle. Due to delays in the path of the control signal and the delay through the bus driver between an internal bus and the data bus, the data to be written are put on the data bus and are guaranteed determinate 40 nanoseconds after the rising edge of E and remaining stable for 25 nanoseconds after E falls. These signals are available to control the memory. We note, however, that R/W does not have a rising edge whose timing can be depended on. R/W is not a timing signal You cannot depend on it to satisfy setup and hold times. Similarly, address signals are not precisely aligned with the memory cycle. Such timing signals are often required and can be obtained by ORing the R/W with the inverted E clock or ANDing E with the AND of various address signals or their complements. Alternatively,the 'A4 chip select signals can be used; see §6.2.2,
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Figure 3.7. Timing Requirements of the Motorola MC68HC912B32
