Figure 9.6. Transmitter Signals

9.3.3 The ACIA

The asynchronous communications interface adapter (AC/A) is a UART that has been specially tailored for use as an external chip for the 6812 microcomputer in normal expanded narrow mode. This section covers the ACIA's highlights. A complete description is available in the ACIA data sheet. The ACIA is designed for the Motorola microcomputer. It can also be used in other microcomputers, and other microcomputer manufacturers have special chips like the ACIA for their systems. The ACIA is different from a UART like the IM6403 in the following ways. To save pins, a bit of the transmitter buffer input, a bit of the receiver buffer output, a bit of the control register, and a bit of the buffer and error status register output are internally connected and then connected to a single pin on this chip. Thus, only 8 pins are used to connect to the data bus. An external clock is needed to set the baud rate, and the transmitter can have a different clock than the receiver. Also, because this chip is designed to connect to a modem, discussed in the next section, it has three pins to control the modem so that the program can control it. Finally, it has a status register with interrupt request logic so that the 6812 can easily examine it in its interrupt handler. (A diagram of the ACIA is shown in Figure 9.7; for simplicity, the system is configured so that this chip is addressed at locations 0x200 and 0x201.)

The transmitter, with its buffer and shift register, and the receiver and its shift register, operate just as in the UART. They are addressed in the same location because the transmitter buffer is write-only, while the receiver buffer is read-only. Once the control register is set up, a word is transmitted simply by writing it in location 0x201, and an incoming word is picked up by reading it from location 0x201.

The 'A4 is configured in narrow extended bus mode to provide data and address buses, E, RW, and CSO. Review §6.4 to determine how to slow the E clock to satisfy the 2-MHz MC68B50's bus timing, and how to provide the data, address, and control signals. As discussed in §8.2.2, timer device 0 provides its transmit and receive clocks for 1200 baud; they are 19.2 KHz (52.08 us or 52 E clock cycles per interrupt). We want to send 8 data bits, even parity, and 1 stop bit. No interrupts are generated, and RTS is low. Consult Table 9.2; bits 7 to 5 should be F (0) to disable interrupts and set RTS low; bits 4 to 2 should be TTF (110) to select 8 data bits, even parity, and 1 stop bit; and bits 1 and 0 should be FT (01) to divide the clock rate, 153.6 KHz, by 16, to deliver 1200 baud. The control word should be 0x19. The instructive pattern OxC5 is

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The receiver is a standard UART receiver with an address comparator, A 7-bit address sent as the low-order 7 bits of an 8-bit word, the most significant bit being true. The tation has a 7-bit address, which is selected by strapping pins 10 to 4 low if a 0 bit is eeded, or leaving them open if a 1 bit is needed in the address (these pins have an nternal pull-up resistor to make them high if they are not connected). If the incoming ddress is equal to the station address, the valid address pulse VAP (pin 31) is made high omentarily, and the station is said to be selected. A 7-bit data word is sent as the lowrder 7 bits of a word, the most significant bit being false. A station that has been elected will put any data word into its receiver buffer when the word is completely hifted in, and make a command strobe CS (pin 32) high momentarily just after this appens. Error status is not available on a pin, but if a parity or framing error is etected, an address will not select a station, data will not be transferred to the receiver uffer, and VAP or CS will not be pulsed.

Note that a typical message will consist of a frame with an address (most significant it [MSB] true) followed by zero or more frames with data, MSB false. A single address ame can be used to trigger a remote station to do something, by asserting VAP in it hen the address is recognized; or a message with an address frame followed by anumber f data frames will cause the data to be stored in the receiver buffer each time a data frame rrives, and will pulse CS to command something to be done with the data.

The transmitter is a conventional UART transmitter modified to send out 16 bits of ata in two consecutive frames if SEND is made high when VAL or CS is asserted (or ithin 8 data bit time units after that) and if it is not currently transmitting a pair of rames. Sixteen bits are sent from the signals on pins 11 to 18 and 29 to 22 by ansferring the data on pins 11 to 18 directly into the transmitter shift register, and imultaneously transferring the data on pins 29 to 22 into the transmitter buffer. The ata in the shift register are sent out (pin 11 data first) in the first UART frame, and the ata in the buffer (pin 29 data first) are sent out immediately after that in the next frame. he data appear on the transmitter output TRO (pin 21) in negative logic. This output is n negative logic so that it can drive a transistor, which inverts the signal to power the nk out of the station.

The chip is designed for both full and half-duplex,with some special provisions for he latter application. In full-duplex applications, a master (likely an ACIA in a icrocomputer) sends to all the slave stations (several Ml4469s) on one line (ACIA xD output to RI input of each slave), while all the slave stations send to the master on nother line (slave TRO output into transistor base; transistor collectors in each slave ed together, in a wire AND bus line, to RxD input of ACIA), so that the master can be ending to a slave at the same time that a slave is sending to the master. In this case, AP can be connected to SEND to send back the two frames as quickly as possible after station is selected. The master should take care it does not send two address frames, one ght after another, so that two slaves will send overlapping frames back. In the halfuplex mode, a single bus line is used between master and all slaves so that the master an send data to the slaves or the slaves can send data to the master, but not at the same me. TxD and RxD in the master, and RI and the transistor collector in each slave, ould be connected to this single line. In this application, SEND should be connected to S so the slave that is selected will wait for an address frame and a data frame to be sent ver the line from the master, before the slave returns its two frames. The master should ait for both frames to be returned before it sends more data on the same line.

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parallel data bus, three handshaking lines, and five control lines. The control lines include one that behaves like the system reset line in the 6812 microcomputer. Others are used to get attention and perform other bus management functions. But the heart of the bus standard is the asynchronous protocol used to transmit data on the bus.

An asynchronous bus protocol uses a kind of expandable clock signal, which can be automatically stretched when the bus is longer or shortened if the bus is shorter. During this process the "clock" is sent from the station transmitting the data to the station that receives the data on one line, then sent back to the transmitter on another line. The transmitter waits for the return signal before it begins another transmission. If the bus is lengthened, so are the delays of this clock signal. The IEEE-488 bus uses this principle a couple of times to reliably move a word on a 9-bit bus from a transmitter to a receiver. (See Figure 9.12.)

The handshake cycle is like a clock cycle. Each time a word is to be moved, the bus goes through a handshake cycle to move the word, as shown in Figure 9.12, The cycle involves negative-logic data available (DAV), sent by the transmitter of the data, and positive-logic ready for data (RFD) and positive-logic data accepted (DAC), sent by the receiver of the data.

If the receiver is able to take data, it has already asserted RFD high. When the transmitter wants to send a data word, it first puts the word on the bus, and then begins the handshake cycle. It checks for the RFD signal. If it is asserted at the transmitter, the transmitter asserts DAV low to indicate the data are available. This is step 1 in Figures 9.14a and 9.14b. When the receiver sees DAV asserted, it negates RFD low in step 2 because it is no longer ready for data. When the processor picks up the data from the interface, the receiver asserts DAC high to indicate data are accepted. This is step 3. When the transmitter sees DAC asserted, it negates DAV high in step 4 because it will soon stop sending data on the data bus. When the receiver sees DAV negated, it negates DAC in step 5. The data are removed sometime after the DAV has become negated. When it is ready to accept new data, it asserts RFD high in step 6 to begin a new handshake cycle.

The IEEE-488 bus (Figure 9-14) is designed for busing data to and from instruments. First, the bus is asynchronous. If the receiver is far away and the data will take a long time to get to it, the DAV signal will also take a long time, and the other handshake signals will be similarly delayed. Thus, long cables are automatically accounted for by the handshake mechanism. Second, the instrument at the receiver may be slow or just busy when the data arrive. DAC is asserted as soon as the data get into the interface, to inform the transmitter that they got there; but RFD is asserted as soon as the instrument gets the data from the interface, so the interface won't get an overrun error that a UART can get. Third, although only one station transmits a word in any handshake cycle, a number of stations can be transmitters at one time or another. Fourth, the same word can be sent to more than one receiver, and the handshaking should be able to make sure all receivers get the word. These last two problems are solved using open collector bus lines for DAV, RFD, and DAC. DAC, sent by the transmitter, is negative logic so the line is wire-OR. That way, if any transmitter wants to send data, it can short the line low to assert DAV. RFD and DAC, on the other hand, are positive logic signals, so the line is a wire-AND bus. RFD is high only if all receivers are ready for data, and DAC is high only when all receivers have accepted data.