Embedded system development and labs for ARM (R. Muresan, 2005)

Embedded Systems Development and Labs; The English Edition

voice data transmission from the MSB (most significant bit) to the LSB (low significant bit). The MSB will always be transferred in the first clock period after the WS signal is toggled. If the data length does not match, the receiver or sender will automatically intercept or fill the data. For more information, please refer to the IIS specification presented in the ScC44BOX User’s Manual.

3. Circuit Design

1) S3C44B0 IIS

(1) Signal Lines

The IIS bus has five lines:

●Serial data input (IISDI): The SD signal line of the IIS bus. Input.

●Serial data output (IISDO): The SD signal line of the IIS bus. Output.

●Left/right channel select (IISLRCK): The WS signal line of the IIS bus. Sampling clock.

●Serial bit clock (IISCLK): The SCK signal line of the IIS bus.

●CODECLK is generally 256 (256fs) or 384 (384fs) times the sample frequency (fs). CLDELEK is obtained from the main CPU clock frequency. The CPU timer registers can be configured through programming. The value for the frequency division can be from 0 to 16.The relationship of CODECLK and sample frequency is shown is Table 6-1. It needs to correctly select the IISLRCK and CODEECLK.

Table 6-1 The Relationship of CODECLK and IISRCK

(2) Registers

There are three registers related to IIS:

●IIS Control Register IISCON. IISCON can access the FIFO ready flag, enable or disable transmit DMA service, enable IISLRCK, IIS prescaler and IIS interface.

●IIS Mode Register IISMOD. IISMOD can select master-slave mode, send-receive mode, active level, serial data bit per channel, select CODECLK and IISRCK.

●IIS Prescaler Register IISPSR.

(3) Data Transfer

Normal mode or DMA mode can be selected for data transferring. In normal mode, the microprocessor transfers data according to the status of FIFO. The microprocessor itself accomplishes the data transfer from FIFO to the IIS bus. The status of FIFO is available via IISFCON register. The data can be directly written into the FIFO register IISFIF. In DMA mode, the DMA controller completely controls the data transfer to/from FIFO. The DMA controller automatically sends/receives data according to the status of the FIFO.

2) UDA1341TS Chip

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The UDA1341TS is a voice CODEC made by Philips. UDA1341TS can convert analog dimensional stereo sound into digital signal and vise versa. It can process the analog signal using PGA (Programmable Gain Access) and AGC (Automatic Gain Control) functions. For digital signals, this chip also provides special DSP functions. UDA1341TS is widely used in MDs, CDs, Notebooks, PCs and Camcoders.

The UDA1341TS provides two groups of voice signal input lines, one group of signal output lines, one group of IIS bus interface lines, and one group of L3 bus lines.

The IIS bus interface lines include clock line BCK, word selection line WS, data input line DATAI, data output line DATAO and voice system clock SYSCLK.

The L3 bus lines includes microprocessor interface data line L3DATA, microprocessor interface mode line L3MODE, microprocessor interface clock line L3CLOCK. The microprocessor can configure the UDA1341TS voice processing parameters and system control parameters through the L3 bus. However, the S3C44B0X has no L3bus and the general I/O ports must be used to connect to the UDA1341TS L3 bus. For the L3 bus time sequence and control methods, please refer to UDA1341TS_datasheet.

3) Circuit Interconnection

The IIS interface circuit is shown in Figure 6-20.

Figure 6-20 IIS Interface Circuit

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Figure 6-20 IIS Interface Circuit

6.3.5 Sample Programs

/*--- function code---*/ /*******************************************************************

*modify:

*comment:

********************************************************************/

void Test_Iis(void)

{

IISInit(); // initialize IIS

Uart_Printf(" press \"R\" to Record..., any key to play wav(t.wav)\n"); if(Uart_Getch()=='R')

Record_Iis(); Playwave(5); IISClose();

}

/*********************************************************************

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*modify:

*comment:

********************************************************************/

void IISInit(void)

{

*modify:

*comment:

******************************************************************/

void Init1341(char mode)

{

/* Port Initialize */

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*modify:

*comment:

********************************************************************/

void _WrL3Addr(U8 data)

{

//PA9:L3D PG6:L3M PG7:L3C for( i=0; i<8; i++ )

{

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}

/*********************************************************************

*halt -- halt operate

*modify:

*comment:

******************************************************************/

void _WrL3Data(U8 data,int halt)

{

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// PA9:L3MODE PG6:L3DATA PG7:L3CLOCK for( i=0; i<8; i++ )

{

}

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6.3.6 Exercises

(1)Write a program that implements the function of adjusting the voice volume via button.

(2)Write a program that implements the recording function.

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Chapter7 Real Time Operation System Labs

7.1 uC/OS Porting Lab

6.3.1 Purpose

●Get familiar with the uC/OS-II porting conditions and uC/OS-II kernel basic architecture

●Understand the steps of porting the uC/OS-II kernel to the ARM processor.

7.1.2 Lab Equipment

● Hardware: Embest S3CEV40 hardware platform, Embest Standard/Power Emulator, PC. ● Software: Embest IDE 2003, Windows 98/2000/NT/XP operation system.

7.1.3 Content of the Lab

Learn how to port the uC/OS-II kernel to the S3C44B0 ARM processor. Test its functionality using the Embest IDE.

7.1.4 Principles of the Lab

1. uC-OS-II File System

The file system of the uC/OS-II real time kernel is shown in Figure 7-1. The application software layer is the code based on the uC/OS-II kernel. The uC/OS-II includes the following three parts:

●Kernel Code: This part has no relationship with the microprocessor. The kernel code includes 7 source files and 1 header file. The 7 source files are responsible for tasks such as: kernel management, event management, message queue management, memory management, message management, semaphore management, task scheduling and timer management.

●Configuration Code: This part includes 2 header files for configuring the number of events per control block and it includes message management code, etc.

●Processor Related Code: Includes 1 header file, 1 assembly file and 1 C file. In the process of porting the uC/OS-II kernel the users need to consider these files.

Application Software

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Porting Code (Microprocessor Related)

Os_cup.h

Os_cpu_a.asm

Os_cup_c.c

Figure 7-1 uC/OS-II File System

2. uC/OS-II Porting Conditions

Porting the uC/OS-II to the ARM processor requires the following conditions:

1) The C Compiler Targeting the Microprocessor Can Generate Reentry Code

Reentry code means that a piece of code can be used by more than one task without fear of data corruption. In another words, this code can be recalled after it was interrupted during the processing.

The following are two examples of non-reentrant and reentrant functions: Int temp;

Void swap (int *x, int *y)

{

temp=*x;

*X=*Y; *y=Temp;

}

void swap(int *x, int *y)

{

int temp; temp=*x; *X=*Y; *y=Temp;

}

The difference between these two functions is that the place for storing the variable temp is different. In the first function, “temp” is a global variable. In the second function, “temp” is a local variable. As a result, the upper function is not reentrant function. The lower function is a reentrant function.

2) Use C Language to Enable/Disable Interrupts

This can be done through the CPSR register within the ARM processor. The CPSR register has a global interrupt disable bit. Controlling this bit can enable/disable interrupts.

3) Microprocessor Supports Interrupts and Supports Timer Interrupts (Ticks)

All of the ARM processor cores support interrupts and they can generate timer interrupts.

4) Microprocessor Provide Hardware Support for Stack Control

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