Introduction to Verilog
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Introduction to Verilog
17.1. Synchronous Test Bench
In synchronous designs, one changes the data during certain clock cycles. In the previous test bench one had to keep counting delays to be sure the data came in the right cycle. With a synchronous test bench the input data is stored in a vector or array and one part injected in each clock cycle. The Verilog array is not defined in these notes.
Synchronous test benches are essential for cycle based simulators which do not use any delays smaller than a clock cycle.
Things to note:
data[8:1]=8'b1010_1101;
The underscore visually separates the bits. It acts like a comment.
if (I==9) $finish;
When the data is used up, finish
x<=data[I]; I<=I+1;
When synthesizing to flip-flops as in an In an @(posedge... procedure,
always use nonblocking. Without that you will be racing with the flip-flops in the other modules.
Example 17 .2
// Synchronous test bench module SynchTstBch:
reg [8:1] data; reg x,clk; integer I;
initial begin
data[8:1]=8'b1010_1101; // Underscore spaces bits. I=1;
x=0;
clk=0;
forever #5 clk=~clk;
end
/*** Send in a new value of x every clock cycle***/ always @(posedge clk)
begin
|
if (I==9) $finish; |
#1; |
// Keeps data from changing on clock edge. |
x<=data[I];
I<=I+1; end
topmod top1(clk, x);
endmodule
Friday, January 05, 2001 9:34 pm |
30 |
Peter M. Nyasulu |