Digital design with CPLD applications and VHDL (R. Dueck, 2000)

8.4 PAL Devices With Registered Outputs

K E Y T E R M S

Register A digital circuit such as a flip-flop or array of flip-flops that stores one or more bits of digital information.

Registered output An output of a programmable array logic (PAL) device having a flip-flop (usually D-type) that stores the output state.

Flip-flops are generally found in programmable logic devices as registered outputs. A register is one or more flip-flops used to store data. Registered outputs in programmable array logic (PAL) devices can be used for the same functions as individual flip-flops.

Figure 8.11 shows the logic diagram of a PAL device with eight registered outputs: a PAL16R8. The fuse matrix is identical to that of a PAL16L8 device; the differences

FIGURE 8.11

PAL16R8 Logic Diagram

342 C H A P T E R 8 • Introduction to Programmable Logic Architectures

This operation is usually performed by serially shifting the data the required number of places and feeding back the last output to the first input of a serial shift register.

Rotation can also be accomplished by a parallel transfer operation. We can load the bits of the input into four D flip-flops in the order determined by two select inputs, S1 and S0. Assume that the binary number S1 S0 is the same as the rotation number in Figure 8.12. Table 8.1 summarizes the contents of the circuit after one clock pulse is applied.

Table 8.1 Rotation to the Right by a Selectable Number of Bits

Sketch a circuit, using gates and flip-flops, that can accomplish this rotation as a parallel transfer function. Briefly explain its operation.

Write the Boolean expression(s) for the circuit.

Show how the circuit can be implemented by a PAL16R4 device by drawing fuses on its logic diagram.

SOLUTION Figure 8.13 shows a parallel transfer circuit (barrel shifter) that will perform the specified rotation. The circuit works by enabling one AND gate in each group of four for each combination of S1 and S0. For example, when S1 S0 00, the rotation is 0 and the leftmost AND gate of each group is enabled, transferring the parallel data into the flip-flops so that DA A, DB B, DC C, and DD D. After one clock pulse, QA

QB QC QD ABCD.

FIGURE 8.13

Example 8.2

Rotation by Parallel Transfer (Barrel Shifter)

Similarly, if S1 S0 10, we select a rotation of 2. The third AND gate from the left is selected in each group of four. This makes the data DA C, DB D, DC A, and DD B appear at the flip-flop inputs. After one clock pulse, QA QB QC QD CDAB.

The same principle governs the circuit operation for the other two select codes. The Boolean equations for the circuit are:

QA S1 S0 A S1 S0 D S1 S0 C S1 S0 B

QB S1 S0 B S1 S0 A S1 S0 D S1 S0 C

QC S1 S0 C S1 S0 B S1 S0 A S1 S0 D

QD S1 S0 D S1 S0 C S1 S0 B S1 S0 A

8.5 Universal PAL and Generic Array Logic (GAL)

K E Y T E R M S

One-time programmable (OTP) A property of some PLDs that allows them to be programmed, but not erased.

Generic array logic (GAL) A type of programmable logic device whose outputs can be configured as combinational or registered and whose programming matrix is based on electrically erasable logic cells.

Universal PAL A PLD based on erasable cells and configurable outputs, much like GAL, but primarily designed to emulate PAL devices, such as PAL16L8.

Output logic macrocell (OLMC) An input/output circuit that can be programmed for a variety of input or output configurations, such as active HIGH or active LOW, combinational or registered. Often just called a macrocell.

In-system programmability (ISP) The ability of a PLD to be programmed through a standard four-wire interface while installed in a circuit.

JTAG port A four-wire interface specified by the Joint Test Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit.

Architecture cell A programmable cell that, in combination with other architecture cells, sets the configuration of a macrocell.

Global architecture cell An architecture cell that affects the configuration of all macrocells in a device.

Local architecture cell An architecture cell that affects the configuration of one macrocell only.

Global clock A clock signal in a PLD that clocks all registered outputs in the device.

There are several limitations of standard low-density PALs. First, these devices are one-time programmable (OTP). Since the AND matrix of a PAL is programmable by blowing metal fuse links, programming is permanent; there is no opportunity to correct or update a design. In development of a new design, where many modifications must be made to the original design, this can be particularly wasteful. Second, standard PAL outputs are permanently configured either as combinational or registered. A given PAL has a certain number of each type of output, which may not be optimum for the design. Third, a standard PAL cannot be programmed while it is installed in a circuit.

A number of low-density PLDs have been developed to address these concerns. Devices such as the PALCE16V8 Universal PAL (Vantis Corporation), and the GAL16V8 and GAL22V10 Generic Array Logic (Lattice Semiconductor)* are based on sum-of-products fuse matrices, just as the earlier-version PALs. However, these devices are based on electrically erasable read only memory (EEPROM or E2PROM) cells, rather than fuses, which allow them to be erased and reprogrammed about 10,000 times. A programmed device will hold its data for about 20 years.

Universal PALs and GALs also have programmable input/output configurations. An I/O pin can be configured as a registered output, a combinational output, or a dedicated input, as required. Additionally, an output can be specified as active-HIGH or active-LOW.

*Vantis has recently been acquired by Lattice, so these devices are really produced by the same company

FIGURE 8.17 (a)

PALCE16V8 Logic Diagram (Courtesy of Lattice Semiconductor Corporation)

FIGURE 8.17 (b)

(PALCE16V8 Logic Diagram