Queue Heads

31

4

3

2

1

0

Queue Head LinkointerP

0

0

Q

T

31

Queue Head ElementointerP

0

VF

Q

T

Table C-1: Queue Head Link Pointer Definition

Bit

Name

Description

0

Terminate — 1 = last QH to be processed. The pointer is invalid

and processing should be discontinued after execution of all

TDs within this queue). 0 = the pointer is valid and the next

descriptor can be processed.

1

QH/TD Select — 1 = QH, 0 = TD. Defines whither the link

pointer references a 8-byte queue head or 16-byte transfer

descriptor, so that decoding can be performed correctly.

3:2

Reserved — must be written as 0s.

31:4

Queue Head Link Pointer — specifies the address of the next

descriptor to be processed in the horizontal list.

Table C-2: Queue Head Element Link Pointer

Bit

Name

Description

0

Terminate — 1 = Terminate (no valid queue entries). 0 = Pointer

is valid (process next TD).

1

QH/TD Select — 1=QH, 0=TD. Defines the definition of the

next descriptor that the link pointer references, so that decod-

ing can be performed correctly.

2

This bit is ignored by UHC.

3

Reserved — must be written as 0s.

31:4

Queue Element Link Pointer — specifies the address of the next

TD or QH to be processed in this queue.

Table C-1: UHC I/O Registers

I/O Address

Register

Register Description

Access

Base + 00-01h

USB CommandRegister — Writes to this register cause the indicated con-

troller action. Bit fields defined are:

• Max Packet selects 32 or 64 byte packet size for bus bandwidth recla-

mation.

• Configure Flag indicates that configuration is complete and has no

affect on hardware.

• Software Debug is used to enable and disable the debug feature.

Related to Run/Stop bit field.

• Force Global Resume causes the host controller to broadcast resume

signaling.

• Enter Global Suspend causes all downstream USB transactions to

cease, resulting in global suspend.

• Global Reset forces the UHC to send 10ms of reset over the USB.

• UHC Reset causes internal timers, counters, state machines, etc., to

their default states.

• Run/Stop permits the host controller to single step USB transactions.

Used in conjunction with Software Debug bit.

Base + 02-03h

USB Status Register — This register provides various status states. The sta-

tus bits are defined below:

• HC Halted indicates that the host controller has stopped executing.

Caused by Run/Stop bit or as a result of an internal error.

• UHC Process Error indicates that a fatal error has occurred when pro-

cessing a TD. UHC automatically sets the Stop bit to halt further TD

execution.

• PCI Bus Error indicates that a serious error has occurred during a PCI

transaction, causing execution to stop.

• Resume Detect set by the UHC when it detects a remote wakeup

from the USB while in suspend.

• USB Error Interrupt indicates that a USB transaction has resulted in

an error condition.

• USB Interrupt is set when a TD completes and the TD’s IOC bit is set.

Base + 04-05h

USB Interrupt Enable — Enables and disables the following sources of

interrupt:

• Short Packet Interrupt Enable

• Interrupt On Complete Enable

Resume Enable

Time-out/CRC Enable

Base + 06-07h

Frame Number — Contains the current frame number and frame list index

value.

Table C-1: UHC I/O Registers

I/O Address

Register

Register Description

Access

Base + 08-0Bh

Frame List Base Address — Contains the base address of the frame list in

memory. Programmable only on aligned 4KB boundaries.

Base + 0Ch

Start of Frame Modify — Contains a value that is added to the start value

of the SOF counter to adjust the number of bit times within a frame.

Default value is 64, which is added to the SOF counter’s default of 11936,

thereby yielding a count of 12000 or 1ms SOF intervals.

Base + 10-11h

Port 1 Status/Control — This register controls the state of root hub port 1

and reflects port status change conditions. The bit fields are:

• Suspend indicates whether the port is currently suspended or not.

• Port Reset indicates whether the port is currently reset or not.

• Low-Speed Device Attached indicates the speed of the attached

device.

• Resume Detect indicates that a remote wakeup has been signaled by

a USB device.

• Line Status these two bits reflect the state of the D+ and D- logic lev-

els to support debug efforts.

• Port Enable/Disable Change indicates that the port has been dis-

abled due to either a device being disconnected or babble or LOA

detected on the port.

• Port Enabled/Disabled indicates whether the port is currently

enabled or disabled.

• Connect Status Change indicates that a device has either been con-

nected or disconnected from the port.

• Current Connect Status indicates whether a device is currently

attached to the port.

Base + 12-13h

Port 2 Status/Control — same definition as Port 1