Библиотека архитектур проекта. Файл var16.Vhd.

library unitslib;

use unitslib.all;

entity reg is

port (c,ec,r:in bit; cout,q0,ql,q2,q3,q4,q5,q6,q7,q8,q9:out bit) ;

end reg;

architecture str of reg is

component inv

port(x: in bit; y:out bit);

end component;

component mnand

port(x, y: in bit; z: out bit);

end component;

component mand

port(x, y: in bit; z: out bit);

end component;

component mor

port(x, y: bit; z: out bit);

end component;

component dcrt

port(d,c,r: in bit; q, nq: out bit);

end component;

for all: inv use entity unitslib .inv(inv_beh);

for all: mnand use entity unitslib.mnand(mnand_beh);

for all: mand use entity unitslib.mand(mand_beh);

for all: mor use entity unitslib.mor(mor_beh);

for all: dcrt use entity unitslib.dcrt(dcrt_beh);

signal s2,s3,s6,s8:bit;signal sl,s4,s7,s9:bit_vector(l to 2); signal s5 : bit_vector(l to 3) ; signal sl0: bit_vector(l to 10) ;

begin

dl inv port map(c, s1(1) ) ;

d2 inv port map(r, sl(2));

d3 mnand port map(s1(1),ec, s2);

d4 inv port map(s2, s3);

d5 dcrt port map(s9(2) ,s3,sl(2) , s4 (1) ,s4 (2) ) ;

d6 mor port map(s7(1) ,s4 (1) , s5(D);

d7 dcrt port map (s4 (1) , S3, si (2) , s5 (2 ) , s5 (3 ) ) ;

d8 mand port map(s5(l),s5(2), s6);

d9 dcrt port map(s6,s3,si(2) , s7 (1) ,s7 (2) ) ;

d10 dcrt port map(s7(1),s3,si(2), s8,s9(2));

d11 dcrt port map (s8, s3, si (2) , s9 (1) , s9 (2 ) ) ;

d12 inv port map(s9(l),cout);

d13 mnand port map(s9(1) ,s9 (2) ,sl0(l))

d14 mnand port map(s7(2),s8,sl0(2));

d15 mnand port map(s7(1) ,s5 (2) ,sl0(3))

d16 mnand port map(s5(1) ,s4 (2) , sl0(4))

d17 mnand port map(s9(1) ,s4 (1) ,sl0(5))

d18 mnand port map(s8,s7(1),sl0(6));

d19 mnand port map(s7(1) ,s9 (2) ,sl0(7))

d20 mnand port map(s7(2),s5(1), sl0(8))

d21 mnand port map(s4(1) ,s5 (2) , sl0(9))

d22 mnand port map(s4(2) ,s9 (2) , sl0(10));

d23 inv port map(sl0(l), q9)

d24 inv port map(sl0(2), q8)

d25 inv port map(sl0(3), q7)

d26 inv port map(sl0(4), q6)

d27 inv port map(sl0(5), q5)

d28 inv port map(sl0(6), q4)

d29 inv port map(sl0(7), q3)

d30: inv port map(sl0(8), q2) ;

d31: inv port map(sl0(9), ql);

d32: inv port map(sl0(10), q0);

end str;

architecture rtl of reg is

component dcrt

port(d,c,r:in bit;q,nq:out bit) ;

end component;

for all: dcrt use entity unitslib.dcrt(dcrt_beh);

signal s2,s3,s6,s8: bit; signal sl,s4,s7,s9: bit_vector(l to 2);

signal s5: bit_vector(l to 3); signal sl0: bit_vector(l to 10); begin

dl si(1)<=not с;

d2 si(2)<=not r;

d3 s2<=not (si (1) and ec);

d4 s3<=not s2;

d5 dcrt port map (s9 (2) , s3 , s1 (2) , s4 (1) , s4 (2 } } ;

d6 s5 (1) <= (s7 (1) or s4 (1) ) ;

d7 dcrt port map (s4 (1) , s3 , s1 (2) , s5 (2 ) , s5 ( 3 ) } ;

d8 s6<=(s5(l) and s5(2));

d9 dcrt port map(s6,s3,si(2) , s7(1) ,s7 (2) } ;

dl0 dcrt port map(s7(1) ,s3,s1 (2) , s8,s9(2));

dll dcrt port map(s8,S3,si(2) , s9 (1) ,s9 (2) ) ;

d12 count<=not s9(l);

d13 sl0(1)<=not(s9(1) and s9(2))

d14 sl0(2)<=not(s7 (2) and s8);

d15 sl0(3)<=not (s7 (1) and s5(2))

d16 sl0(4)<=not(s5 (1) and s4(2)}

d17 sl0(5)<=not(s9(1) and s4(l))

d18 sl0(6)<=not(s8 and s7(l));

d19 sl0(7)<=not(s7(1) and s9(2))

d20 sl0(8)<=not(s7(2) and s5(D)

d21 sl0(9)<=not(s4(1) and s5(2))

d22 sl0(10)<=not(s4(2) and s9(2));

d23 q9<=not sl0(l)

d24 q8<=not sl0(2)

d25 q7<=not sl0(3)

d26 q6<=not sl0 (4)

d27 q5<=not sl0 (5)

d28 q4<=not sl0(6)

d29 q3<=not sl0(7)

d30 q2<=not sl0 (8)

d31 ql<=n0t sl0(9)

d32 q0<=not sl0 (10)

end rtl;