Процедурное моделирование. Файл для процедурного моделирования.Файл test.Vhd.

entity test is

end test;

library var16;

use var16.all;

use std.textio.all;

architecture beh_test of test is

component tl

port(c,ec,r:in bit;cout:out bit;q:out bit_vector(0 to 9));

end component;

for all: tl use entity var16.reg(str);

signal с,ее,r,cout:bit; signal q:bit_vector(0 to 9);

begin

crl:tl port map(c,ec,r,cout,q);

process

begin

c<='0','l' after 5ns,'0' after 10ns, 'l' after 15ns,'0' after 20ns,'1' after 25ns,

'0' after 30ns,'1' after 35ns,'0' after 40ns,'I1 after 45ns,'0' after 50ns,

'1' after 55ns,'0' after 60ns,'1' after 65ns,'0' after 70ns,'1' after 75ns,

'0' after 80ns,'I1 after 85ns,'0' after 90ns,'1' after 95ns,'0' after 100ns,

'1' after 105ns,'0' after 110ns, 4' after 115ns,'0' after 120ns; ec<='0','l' after 45ns,'0' after 55ns ; r<='1 ' , '0' after 5ns; wait ;

end process;

process

variable 11:line,

variable t,i:time;

variable n:integer:=0;

begin

t:=now;

if t=2ns then

if n=0 then

write(11,"time с ec r Q(0 to 9) cout");writeline(output,11)

n: = 1 ;

end if ;

end if;

i:=2ns;

if t=i then

write (11, t;) ; writedl," ") ; write (11, c) ; write(ll," "} ; write(11,ec) •

write(11," "); write(11,r); writedl," "); write (11, q ( 0) ),writedl,q(l) ) ;

writedl,q(2) ); write (11, q (3 )); write (11, q (4 ) ) ; write (11, q ( 5 ) ) write(11,q(6) ) ;

write (11,q (7) ) ; write (11, q (8) ) ; write (11, q ( 9 ) ) ; writedl," ") write(11,cout);

writeline(output,11);

i:=i+5ns;

end if; wait for Ins;

end process;

end beh_test;

Команды выполнения процедурного моделирования.

vhdl unitslib.vhd

vhdl var16.vhd

vhdl test.vhd

link test test test

sv 120ns test

Результат процедурного моделирования.

time с еc r Q(0 to 9) cout

2ns 110 1000000000 1

7ns 011 1000000000 1

12ns 11 1000000000 1

17ns 01l 0100000000 1

22ns 111 0100000000 1

27ns 01l 0010000000 1

32ns 111 0010000000 1

37ns 01l 0001000000 1

42ns 111 0001000000 1

47ns 001 0001000000 1

52ns 101 0001000000 1

57ns 01l 0000100000 0

62ns 111 0000100000 0

67ns 01l 0000010000 0

72ns 111 0000010000 0

77ns 01l 0000001000 0

82ns 111 0000001000 0

87ns 01l 0000000100 0

92ns 111 0000000100 0

97ns 01l 0000000010 0

102ns 000 0000000010 0

107ns 100 0000000001 1

112ns 000 0000000001 1

117ns 100 1000000000 1

Интерактивно-графическое моделирование.

Стенд регрессионного тестирования структурной и потоковой архитектур.

Файл gtest.vhd.

library var16;

use var16.all;

entity gtest is

end gtest ;

architecture beh_t of gtest is

component tl

port(c,ec,r:in bit;cout:out bit;q:out bit_vector(0 to 9});

end component;

component t2

port(c,ec,r:in bit;cout:out bit;q:out bit_vector(0 to 9));

end component;

for all: tl use entity var16.reg(str);

for all: t2 use entity var16.reg(rtl);

signal c,ec,r:bit;

signal q, ql:bit_vector(0 to 9);

signal cout,coutl:bit;

begin

al:tl port map(c,ec,r,cout,q);

a2:t2 port map(с,ec,r,coutl,ql) ;

process(cout,coutl,q,ql)

begin

assert cout=coutl report "cout/=coutl" severity error; for i in 0 to 9 loop

assert q(i)=ql(i) report "q/=ql" severity error;

end loop;

end process;

end beh_t;