Cadence / DSD2 / Конспект -Введение в Cadence DSD2 / Конспект -Введение в Cadence DSD2 / введение_cad / auto.4

Cadence Tutorial

Example : Automatic Layout Generation (CMOS Inverter) Step 4 : Finishing Touches

At this point the design is almost finished. Unfortunately the automatic design creation process for this fabrication technology is unable to add substrate connections. So these will have to be added by the user.

1. Using the Create --> Instance command select a PTAP substrate contact.

Place the instance close to the bottom of the NMOS transistor, close to the source region (which has not been connected to a ground rail yet).

2. Using the Create --> Instance command select a NTAP substrate contact.

This contact will be used as the n-well contact.

As in the previous manuallayout example, the N-Substrate contact will not fit in a n-well that is drawn according to the minimum distance rules from the transistor. Since the transistor is an instance, it is not possible to stretch the n-well edge as it has been done in the layout example.

To address this problem, we can easily draw an extension to the already existing n-well using the rectangle command.

The next step is to draw the ground rail and the power rail.

3. Using the Rectangle command draw the ground rail with Metal-1.

Make sure to connect the NMOS source and the substrate contact to the ground rail you have just drawn.

4. Draw the power rail with Metal-1.

Notice that the power rail and the ground rail are symmetric. So instead of redrawing the power rail you can copy the ground rail.

To select multiple objects press "SHIFT" key while selecting objects. When you are done, use Edit --> Copy command to copy the selected image. You can flip the selected image upsidedown by clicking the "upsidedown" button on the copy dialog box.

5. Place the pins.

The next step is to give connection information to the power rails and ground rails. To do this, first select the Metal-1 layer from the layer selection window and then use the Create --> Pin command.

This will pop-up a dialog box to allow you enter various parameters of the pin.

For the power rail enter the name: "vdd!" (without quotes, watch case and the exclamation mark). The exclamation mark is important, it defines a global signal, that is a signal name that is unique accross your entire design.

Define a rectangle with the Metal-1 layer on the power rail, as the pin location. The location of the pin and the size are not relevant (at least not in this context), as a good practice try to make it a minimum sized box (0.9u x 0.9u) and make sure it is on the power rail. Place a pin on the ground rail in a similar way. Use the name "gnd!" (without the quotes, watch for the case and exclamation mark) for the pin name.

Place the pin:

This is the final layout, created by the automatic device level editor.

a production of

Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134.

Please read this DISCLAIMER

Last Updated by Ilhan Hatirnaz on 11/15/1998