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Cadence Tutorial

Example : Automatic Layout Generation (CMOS Inverter) Step 1 : Starting the Automatic Layout Tool

To start the automatic layout generation, you must have finished your circuit schematic first. Please follow the Schematic Tutorial Example first if you have not done so.

1. Open the schematic view of your design.

In this example, the PMOS transistor has a channel width of W=4.5u and a channel length of L=0.6u, while the NMOS transistor has a channel width of W=3u and a channel length of L=0.6u.

2. From the menu select Tools --> Design Synthesis --> Device-Level Editor.

Selecting this option will first open up a small dialog box that will let the user select the cell name for the layout. It is a good idea to use the same cell name and specify layout as the cell view name.

Upon the selection of the view name, the user will be prompted another small dialog box. This box will ask for a pin layer, pins in the layout will be placed as connections in the given layer. Choose Metal-1 as the I/O Pin Layer, and all of the pins that you have specified in your schematic will be placed as connections in Metal-1.

In addition to the already open schematic window, a new layout window and the layer selection window will pop up. These three windows define the working environment for the automatic layout generation flow.

After the I/O pin layer is selected, two rectangles representing the transistors (the nmos and the pmos) and two Metal-1 squares will show up in the bottom half of the layout window. Notice the cyan colored square on the upper half of the layout window: This is the estimated size of the layout, this size is not mandatory, it is calculated roughly from the sizes of the active elements.

With the next step, you'll start forming the layout within the box above.

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Last Updated by Ilhan Hatirnaz on 11/15/1998