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Cadence Tutorial

Scalable Sub-micron Design Rules

The following rules are taken from the MOSIS webpage:

http://www.mosis.org/New/Technical/Designrules/dr-scmos72.html Please note that the following rules are SUB-MICRON enhanced lambda based rules. Only rules relevant to the HP-CMOS14tb technology are presented here. In addition to the lambda rules, the micron rules for lambda=0.3u are given in an additional column. Please refer to http://www.mosis.org/New/Technical/Designrules/dr-scmos72.html for more accurate and complete information.

Layout Rules 1. Well 2. Active 3. Poly 4. Select 5. Poly Contact 6. Active Contact 7. Metal-1 8. Via 9. Metal-2 14. Via2 15. Metal-3 1. Well RuleDescription LambdaMicrons 1.1Minimum width123.6u 1.2Minimum spacing between

wells at different potential185.4u 1.3Minimum spacing between

wells at same potential61.8u

2. Active RuleDescription LambdaMicrons 2.1Minimum width30.9u 2.2Minimum spacing30.9u 2.3Source/drain active to well edge61.8u 2.4Substrate/well contact active to well edge30.9u 2.5Minimum spacing between

active of different implant0 or 40 or 1.2u

3. Poly RuleDescription LambdaMicrons 3.1Minimum width20.6u 3.2Minimum spacing30.9u 3.3Minimum gate extension of active20.6u 3.4Minimum active extension of poly30.9u 3.5Minimum field poly to active10.3u

4. Select RuleDescription LambdaMicrons 4.1 Minimum select spacing to

channel of transistor30.9u 4.2 Minimum select overlap of active20.6u 4.3 Minimum select overlap of contact10.3u 4.4 Minimum select width and spacing20.6u

5. Poly Contact RuleDescription LambdaMicrons 5.1Exact contact size 2x20.6u x 0.6u 5.2bMinimum poly overlap10.3u 5.3Minumum contact spacing30.9u 5.4Minimum spacing to

gate of transistor20.6u 5.5bMinimum spacing to other poly51.5u 5.6bMinimum spacing to active

(single contact)20.6u 5.7bMinimum spacing to active

(multiple contacts)30.9u

6. Active Contact RuleDescription LambdaMicrons 6.1 Exact contact size 2x20.6u x 0.6u 6.2b Minimum active overlap 10.3u 6.3 Minimum contact spacing30.9u 6.4 Minimum spacing to gate of transistor 20.6u 6.5b Minimum spacing to diffusion active 51.5u 6.6b Minimum spacing to field poly

(single contact) 20.6u 6.7b Minimum spacing to field poly

(multiple contacts) 30.9u 6.8b Minimum spacing to poly contact 41.2u

7. Metal-1 RuleDescription LambdaMicrons 7.1Minimum width 30.9u 7.2aMinimum spacing30.9u 7.3Minimum overlap of any contact10.3u

8. Via RuleDescription LambdaMicrons 8.1Exact size2 x 20.6u x 0.6u 8.2Minimum spacing30.9u 8.3Minimum overlap by Metal-110.3u 8.4Minimum spacing to contact20.6u

9. Metal-2 RuleDescription LambdaMicrons 9.1Minimum width30.9u 9.2bMinimum spacing30.9u 9.3Minimum overlap of via110.3u

14. Via2 RuleDescription LambdaMicrons 14.1Exact size 2 x 20.6u x 0.6u 14.2Minimum spacing 30.9u 14.3Minimum overlap by Metal-210.3u 14.4Minimum spacing Via-120.6u

15. Metal-3 RuleDescription LambdaMicrons 15.1Minimum width51.5u 15.2Minimum spacing30.9u 15.3Minimum overlap of Via-220.6u

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