Перевод МММ / 13 %%% ecs10_sige_snps Moroz

Towards the end of CMOS roadmap, both Ge and III-V channel materials become inferior to Si due to their larger quantum separation, lower density of states, and inferior transport properties for the required channel sizes.

Fig. 12. Opportunity window for non-Si channel materials based on projected stress engineering and carrier transport analysis.

Conclusions

Evolution of stress engineering techniques is explained with respect to the changing relative proportions and aspect ratios of different parts within transistor and its surrounding. Stress-induced defects are reviewed along with the guidelines on minimizing harmful stress levels during critical parts of the process flow. Conversion of stress-enhanced mobility into transistor’s driving current is discussed as a function of channel length and process optimization.

FinFET-specific stress engineering is described with a demonstration of achieving 5 GPa channel stress by using known stress sources. Comparative analysis of alternative FinFET stress sources is given. The combination of SiGe transport properties and appropriate stress engineering shows advantage of using SiGe channel material. Longer term, towards the end of CMOS roadmap, Si becomes superior to the SiGe, Ge, and III-V channel materials for a variety of reasons.

Three-dimensional simulation can be used to balance the trade-offs and optimize transistor design for each technology node and particular process flow. One of the important applications where numerical stress analysis is instrumental is how to maximize the amount of beneficial stress near the source side of channel while minimizing harmful stress levels everywhere else.

References

1.S. Natarajan et al., IEDM Tech. Dig., p. 941 (2008).

2.V. Moroz et al., to be presented at ECS 2010 Symposium on High Purity Silicon.

3.V. Moroz et al., Solid-State Tech., July (2004).

4.Sentaurus TCAD tools, v. 2010.03, Synopsys (2010).

5.Y. Liang et al., J. Appl. Phys., 97, 043519 (2005).

6.C.S. Smith, Phys. Rev., 94, 42 (1954).

7.Y. Kanda, IEEE Trans. Electron Dev., ED-29, 64 (1982).

8.B. Obradovic et al., IWCE Proc., 26 (2004).

9.L. Smith et al., Electron Dev. Lett., 26, 652 (2005).

10.S. E. Thompson et al., IEDM Tech. Dig., 27.1 (2006).

11.L. Washington et al., Electron Dev. Lett., 27, 511 (2006).

12.L. Smith et al., MRS Proceedings (2007).