Перевод МММ / 13 %%% ecs10_sige_snps Moroz

Strain Scaling and Modeling for FETs

Victor Moroz and Munkang Choi

Synopsys, Inc., 700 East Middlefield Road, Mountain View, California 94043, USA

Stress engineering overview is given including the reasons behind its ongoing evolution. Some aspects of the stress-induced defect formation are discussed. Guidelines for avoiding such defects are proposed based on stress evolution in and around transistors during the process flow. Stress-induced performance is addressed with the focus on conversion of stress-enhanced mobility into stressenhanced on-state current. FinFET-specific stress engineering is analyzed as well as the stress vs capacitance trade-offs. Usage of simulation tools for optimization of various stress-related design trade-offs is demonstrated. It is concluded that it is a pursuit of beneficial stress patterns that improve transistor performance without creating defects and increasing variability that defines evolution of stress engineering techniques.

Introduction

Stress engineering has become an enabler of continuing transistor scaling. State-of-the-art transistors have over 2 GPa stress in the channel that triples hole mobility and doubles PMOS driving current. Due to such prominent performance boost, stress engineering will likely continue to be used in the foreseeable future either for silicon or non-silicon channel materials.

Transistor scaling simplifies stress engineering in some respects, but complicates it in other respects. If all parts of a transistor, a contact, and shallow trench isolation (STI) were scaled similarly, then any proven stress engineering methodology can keep bringing similar benefits across several technology nodes. However, for many reasons different active and passive components experience quite different shrinking factors from one node to the next. This changes relative efficiencies of different stress sources.

For example, a combination of larger relative spacer width, larger relative source/drain elevation, and slot contact being introduced instead of the conventional point contact, severely reduce the amount of channel stress that can be delivered by a strained contact etch-stop layer (CESL). Moreover, introduction of gate-last high-k metal gate (HKMG) process virtually eliminates CESL-induced channel stress. This dictates reduced usage of strained CESL and dual strained liner (DSL) in the industry.

An opposite example is SiGe source/drain. Slow scaling of SiGe source/drain depth combined with higher Ge content can induce higher channel stress for a shrank transistor. The gate-last HKMG process further increases SiGe-induced stress [1], although this benefit happens only once upon introduction of the gate-last process and can not be scaled further.

The flip side of stress engineering is that stress is only useful inside the part of channel that is within 2 nm from the channel surface and is adjacent to the source junction. There, it enhances carrier mobility and therefore boosts transistor’s performance.

Stress can be also marginally useful in improving source/drain contact resistance, but this effect is too small to warrant special stress engineering techniques targeting it. Everywhere outside of that small portion of the channel, stress is harmful.

One major harmful stress-related effect is that it shrinks silicon bandgap, which increases junction leakage. For example, stress that is in the channel part that is adjacent to the drain junction does not contribute to the performance boost, because there carrier transport is determined by the stress-independent velocity saturation mode. That particular area is the epicenter of drain junction leakage. Stress within that area increases junction leakage by a factor of about 5x per GPa of compressive uniaxial stress [2]. Therefore, any stress in that area degrades the off-state current without enhancing the onstate current.

Another major harmful stress-related effect is defect formation. Most of the stress sources that are used for stress engineering are located outside of the channel. For any stress source to introduce certain stress level into the channel, the stress level inside and immediately around the stress source has to be higher than in the channel, because stress always decays outside of the stress source. Typically a stress source delivers to the channel less than 50% of its nominal stress [3]. Therefore, a stress source of over 2 GPa is necessary to create a 1 GPa channel stress.

One important side effect of this observation is that it is preferable to split stress engineering into several moderate strength sources instead of a single monster stress source. All separately generated stresses sum up in the channel as a linear superposition, so that the maximum stress is inversely proportional to the number of stress sources employed.

The problem with high stress levels somewhere close to the stress sources is that they can create various defects that might degrade or even disable transistors. The next section addresses this issue.

Stress-Induced Defects

How much stress is too much? Figure 1 shows TEM image of a PMOS transistor with a crippling defect in the channel. The defect is believed to be a vacancy-type {111} stacking fault that occurs at high temperature anneal in silicon subject to high level of compressive stress. For such stacking fault to form, a large number of silicon atoms have to move around. This is only possible during a high temperature anneal. Therefore, stress sources that are created before the high temperature process annealing steps such as activation of implanted dopants have an inherently higher probability of introducing crystal defects.

cCESL

Fig. 1. TEM image of a 33nm pMOSFET with SiGe source/drain and CESL with compressive stress.

An example of such stress source would be SiGe source/drain epitaxy that is often followed by implants and high temperature anneals. Using in-situ doped SiGe epitaxy that is done at a moderate temperature would suppress this undesirable effect.

Any approach that postpones introduction of high stress levels until after the high temperature steps will suppress defect formation and improve yield. One interesting example is the usage of gate-last HKMG process to postpone a large portion of the SiGe source/drain stress until the completion of front-end process flow. Specifically, the SiGe source/drain epitaxy does introduce some stress before the anneal, but removal of dummy poly gate after the anneal significantly increases the amount of SiGe-induced channel stress [1] when it is too late for the crystal defects to form.

The mechanism behind SiGe-induced stress is lattice mismatch that accumulates along the Si/SiGe interface. The amount of SiGe stress is a strong function of the SiGe volume and the Si/SiGe interface area. Figure 2 shows a huge difference (by a factor of 3.8) between lateral stress levels induced by a blanket SiGe epitaxy over an entire wafer vs local 100 nm deep and 50 nm wide SiGe island that is similar to a typical source/drain size. The stress levels are calculated for 2D structures with Sentaurus Process simulator [4].

Similar results have been recently obtained experimentally, with the critical SiGe thickness increasing 10-fold from 20 nm to 200 nm by growing SiGe with 45% Ge on a 12 nm thin silicon membrane vs standard silicon wafer [5].

Fig. 2. Calculated lateral stress in the middle of the blanket and local 100 nm thick SiGe epitaxial layers.

Therefore, it is possible to keep increasing Ge content in a selectively grown small SiGe islands well beyond critical thickness as long as appropriate design rules are followed to avoid large variation of SiGe sizes on the same chip.

Stress-Induced Performance Boost

Stress-enhanced mobility has been extensively studied over the last 56 years, especially for the last decade [6-10]. Figure 3 illustrates conversion of stress-enhanced mobility into stress-enhanced on-state current obtained with Sentaurus Device [4].

Fig. 3. Calculated conversion of stress-enhanced mobility to stress-enhanced on-state current. The stars illustrate typical conversion values observed for different technologies.

At large channel lengths, the on-state current gain is the same as the mobility enhancement. Unfortunately, as the channel length shrinks for a given process, the onstate gain reduces. Fortunately, process is modified for each technology node, keeping the conversion factor at 0.5 +/-0.1 [8, 11].

This happens because the on-state current is determined by a combination of mobility-limited carrier transport near source junction and velocity saturation limited carrier transport near drain junction. The long channel transistors operate almost entirely in mobility-limited carrier transport mode, because drain junction depletion region width is negligible compared to the channel length. For shorter channel lengths, the dominant carrier transport mechanism switches from stress-enhanced mobility to the stressindependent velocity saturation.

A transistor can be designed such that it is located anywhere in terms of the Fig. 3 coordinates. However, typical transistor design across the industry keeps the balance around the factor of 0.5, which means that about 50% of drain current is determined by mobility-limited carrier transport, with the other 50% coming from stress-independent velocity saturation carrier transport. Apparently, this balance is instrumental in achieving the best possible Ion/Ioff ratio.

This effect should be carefully considered when designing next generation transistors such that they get enough benefit from stress engineering despite the undesirable direction of the trends depicted on Fig. 3.

The overwhelming majority of stress engineering research has been done for planar transistors, whereas the FinFETs that are expected to be introduced at 15 nm technology node received very limited amount of attention so far. The next section addresses several facets of FinFET stress engineering.

FinFET Stress Engineering

Considering that FinFET transistor architecture is expected to replace the planar MOSFETs around 15 nm node, we analyze which stress engineering techniques can be successfully applied to a FinFET. The FinFETs exhibit a whole new optimization space, including trade-offs between stress engineering, source/drain resistance, parasitic capacitance, and design rules.

Figure 4 illustrates a 15 nm FinFET with epitaxially merged fins outside of the gate stack. This selective in-situ doped source/drain epitaxy using SiGe for PMOS and Si:C for NMOS simultaneously improves beneficial channel stress and source/drain conductance, but degrades parasitic gate-to-drain capacitance.

Fig. 4. 15nm FinFET with epitaxially merged source and drain fins.

Figure 5 shows FinFETs with SiGe source drain elevation increasing from 2 nm for the upper left FinFET up to 12 nm for the lower right FinFET with 2 nm increments. The SiGe has 20% Ge and {111} facets around all fin corners.

Fig. 5. 15nm FinFET with different amount of epitaxial elevated SiGe source/drain. From top left towards lower right, the source drain elevation changes from 2 nm to 12 nm in increments of 2 nm.

Figure 6 shows stress averaged across the fin channel for all 6 FinFETs from Fig. 5. The main beneficial stress components, compressive longitudinal Sxx and tensile transverse Szz almost double as the elevation increases from 2 nm to 12 nm. Fortunately, the Syy stress component that is mostly irrelevant for PMOS stress engineering is low and therefore harmless.

Fig. 6. Dilatational stress components averaged across the channel for different amounts of epitaxial SiGe source/drain elevation Helev. The SiGe has 20% Ge.

Figure 7 shows evolution of stress-enhanced mobility and parasitic gate-to-drain capacitance as a function of source/drain elevation. The mobility increases by 15% and saturates at that level for elevations above 10 nm. The capacitance increases faster up to 17% at 6 nm elevation, but then decreases because the adjacent fins merge and reduce the relevant surface area.

Fig. 7. Trade-off between stress engineering and parasitic capacitance as a function of epitaxial source/drain elevation Helev. The delay is calculated as CV/I.

The competing stress engineering and parasitic capacitance slow down transistor (in terms of CV/I) by 6% at the 4 nm and 6 nm source/drain elevations, but then produce a dramatic switch to a 5% faster transistors at 10 nm and 12 nm elevation levels. This example shows complexity and 3D nature of FinFET optimization trade-offs. Threedimensional simulation can be used to balance the trade-offs and optimize transistor design for each technology node and particular process flow.

Due to the fully-depleted channels and better gate control, FinFETs open an opportunity window for high mobility non-Si channel materials that exhibit poor shortchannel behavior in planar MOSFETs. Figures 8 and 9 show one of the options for implementing high-mobility epitaxial channel into a 15nm FinFET.

Figure 10 illustrates typical stress distributions inside the SiGe channel layer and inside the Si core fin. The stress is coming from the 2.5 nm thick SiGe channel layer with 20% Ge. The SiGe epi layer has beneficial compressive longitudinal stress but detrimental compressive transverse stress. The core Si fin has the opposite stress signs, with detrimental longitudinal tensile stress and beneficial transverse tensile stress.

Overall, the impact of all these stress components combined is positive, summarized on Fig. 11. There, a FinFET with SiGe epitaxial channel exhibits 1.8x higher Idlin than the reference Si FinFET, with the gain reducing down to 1.5x as the drain bias increases towards Vdd=0.5 V. This happens due to the very high low-field mobility in SiGe switching to an inferior SiGe velocity saturation at high drain biases. The stress almost doubles the drain current, with similar gain reduction towards high drain bias levels.

Fig. 8. Current density pattern in a FinFET with high-mobility channel material in the onstate mode.

Fig. 9. Current density pattern in a FinFET with high-mobility channel material in the off-state mode.

Fig. 10. Distributions of longitudinal Sxx, transverse Szz, and normal Syy stress components along the cut-lines going through epitaxial SiGe layer and the core Si fin.

Fig. 11. Drain current enhancement of a FinFET with SiGe epitaxial channel layer compared to a FinFET with stress-free Si channel. The “without ” curve only accounts for the faster carrier transport in a stress-free SiGe compared to a stress-free Si. The “with” curve also accounts for the stress-enhanced carrier transport in SiGe.

One of the open issues in FinFET design is how much stress it is possible to introduce into the channel. We found that a SiGe source/drain is very effective at delivering beneficial stress pattern into the channel, with 33% Ge creating -3.08 GPa compressive longitudinal stress averaged over the entire volume of fin channel. This, combined with the stress coming from 2.5 nm thick SiGe epitaxial channel layer with 20% Ge and with 1 GPa tensile stress in replacement metal gate, gives Sxx=-5.08 GPa, Syy=-0.24 GPa, and Szz=-0.20 GPa inside the SiGe channel and Sxx=-2.40 GPa, Syy=0.13 GPa, and Szz=1.69 GPa inside the core Si fin.

Most likely, 5 GPa stress is too risky for practical purposes (see Fig. 1), but the point here is that there are existing methodologies that can deliver that much stress if necessary.

In terms of relative efficiency of these stress sources, the 1 GPa tensile replacement metal gate only delivers channel stress of the order of 100 MPa, which is almost negligible compared to the other two techniques. The SiGe epi layer creates high stress levels that partially cancel each other’s benefits, which is highly undesirable just because you have potentially harmful stress that is not giving any performance boost. The SiGe source drain exhibits the best stress pattern, with mostly beneficial stress components and not much else. Similar symmetric behavior is expected for a Si:C source/drain for NMOS.

If we combine the stress engineering analysis described above with quantum separation, available densities of states, and carrier transport properties of SiGe, Ge, and III-V channel materials [12], we arrive at the estimated opportunity window shown on Fig. 12. Whereas SiGe and Ge have relatively wide opportunity window, the potential III- V channel materials have much lower chances of being introduced into manufacturing.