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IEEE TRANSACTIONS ON ELECTRON DEVICES

1	Variation Study of the Planar Ground-Plane Bulk
2	MOSFET, SOI FinFET, and Trigate
3	Bulk MOSFET Designs
4	Xin Sun, Victor Moroz, Nattapol Damrongplasit, Changhwan Shin, and Tsu-Jae King Liu
5	Abstract—The impact of systematic and random variations
6 on transistor performance is investigated for the trigate bulk
7	MOSFET, the planar ground-plane bulk MOSFET, and SOI
8	FinFET. The results indicate that the trigate bulk MOSFET design
9 is least sensitive to process-induced variations and offers the best
10 nominal performance, as compared with the planar ground-plane
11	bulk MOSFET and SOI FinFET.
12	Index Terms—Fin-shaped FET, metal–oxide–semiconductor
13	ﬁeld-effect transistor (MOSFET), multigate FET, variability.
14	I. INTRODUCTION
15	ARIABILITY IN transistor performance dramatically in-
16	Vcreases as the critical dimension (the gate length) is
17	reduced well below 50 nm. This poses critical challenges for
18	continued CMOS scaling and cost-effective utilization of scaled
19	technologies [1]. Variations in transistor performance can be
20	divided into two main categories, i.e., systematic and random
21	variations. Sources of systematic variation include process-
22	induced variations in gate length LG, channel width WSTRIPE,		Fig. 1. (a) Three-dimensional view of MOSFET designs studied in this letter.
23	gate oxide thickness tox, and layout-dependent channel stress.		(b) Channel doping proﬁle for trigate and planar ground-plane bulk MOSFETs.
24	Sources of random variation include gate line edge roughness
25	(LER) and random dopant ﬂuctuations (RDF), which are also		(see Fig. 1(b), peaked at a depth tSi with 4-nm/dec doping 39
26	intrinsic sources of variation [2] (i.e., fundamental to the tran-		gradient [6], [8]) is used to improve the electrostatic integrity 40
27	sistor architecture and manufacturing processes).		[3], [6]. For the SOI FinFET, the channel is undoped.	41
28	As candidate structures to extend transistor scaling to its		Sentaurus 3-D device simulations [9] using advanced physi- 42
29	ultimate limit, the planar ground-plane bulk MOSFET, SOI		cal models are performed for the following n-channel MOSFET 43
30	FinFET, and trigate bulk MOSFET structures have been investi-		nominal designs: physical gate length LG = 20 nm, equivalent 44
31	gated [3]–[7]. A comparison of the scale lengths for these struc-		oxide thickness tox = 9 Å, and supply voltage VDD = 0.7 V. 45
32	tures shows that the trigate bulk MOSFET is more scalable than		Three-dimensional quantization effects are included using the 46
33	the other two designs [7]. In this paper, the impact of process-		density gradient quantization model. A hydrodynamic model 47
34	induced variations on transistor performance is investigated for		(ﬁt to Monte Carlo simulation results) is used to model carrier 48
35	each of these structures to see which one is most scalable.		transport [9]. For the trigate bulk MOSFET design, silicon 49
		IEEEstripe width WSTRIPE = LG and two cases of tSi (equal to 50
36	II. NOMINAL MOSFET DESIGNS		oxide recess depth HSTRIPE) are simulated (tSi = 0.6 LG 51
37	The transistor structures are illustrated in Fig. 1. For the pla-		and 0.8 LG) with the source/drain extension junction depth 52
38	nar and trigate bulk MOSFET designs, retrograde well doping		XJ = 1.2 HSTRIPE; for the planar bulk MOSFET design, 53
			same values of WSTRIPE and tSi are assumed, and XJ = 7 nm; 54
			for the SOI FinFET design, WSTRIPE is set to 0.6 LG to 55
	Manuscript received January 18, 2011; revised April 13, 2011 and June 24,		suppress short-channel effects (SCEs), and ﬁn height HSTRIPE 56
			is chosen to achieve the same effective channel width We 57
	2011; accepted June 28, 2011. The review of this paper was arranged by Editor
	S. Deleonibus.		as the Prooftrigate bulk MOSFET design. The trigate and FinFET 58
	X. Sun, N. Damrongplasit, C. Shin, and T.-J. K. Liu are with the Department		designs are assumed to have the same channel stripe pitch 59
	of Electrical Engineering and Computer Sciences, University of California,		(2 LG, which is an aggressive estimation), as this is set by 60
	Berkeley, CA 94720 USA (e-mail: sunxin@eecs.berkeley.edu).
	V. Moroz is with Synopsys, Inc., Mountain View, CA 94043 USA.		lithography limitations. For each design, the effective channel 61
	Color versions of one or more of the ﬁgures in this paper are available online		length (Le , which is modulated by offset spacer width) is 62
	at http://ieeexplore.ieee.org.
	Digital Object Identiﬁer 10.1109/TED.2011.2161479		optimized to minimize intrinsic delay Ctotal VDD/Ie , where 63

2 IEEE TRANSACTIONS ON ELECTRON DEVICES

TABLE I

OPTIMAL DESIGNS FOR THE TRIGATE BULK MOSFET, PLANAR BULK MOSFET, AND SOI FINFET

64	Ctotal is the total gate capacitance, and Ie is the average of
		IEEE
65 the drain current ID for VGS = VDD and VDS = VDD/2 and
66	ID for VGS = VDD/2 and VDS = VDD, at a ﬁxed 18-nA/μm
67 OFF-state leakage current IOFF, as speciﬁed for planar bulk
68	MOSFETs. The ID –VG characteristics of the optimal designs
69	(summarized in Table I) are shown in Fig. 2. The trigate bulk
70	MOSFET design with tSi = 0.6 LG shows the best subthresh-
71 old swing S due to superior gate control. It has 7% lower
72 intrinsic delay than the optimal SOI FinFET and 35% lower
73 intrinsic delay than the optimal planar bulk MOSFET design.
74	III. IMPACT OF SYSTEMATIC VARIATIONS
75	Here, the effects of systematic variations in LG, WSTRIPE
76	(for trigate and FinFET structures), tox, and channel stress
77 distribution (for trigate and planar MOSFETs) are discussed.
78	Fig. 3 shows threshold voltage (VT , which is deﬁned as
79 the voltage, where drain current ID is 100 nA We /LG)
80 sensitivity to LG variation. For tSi = 0.6 LG, VT variation in
81 the trigate bulk MOSFET design is the smallest among the three
82 structures. For tSi = 0.8 LG, however, it increases to the same
83 level as that of the planar bulk MOSFET design due to degraded
84 electrostatic integrity [7].
85	For the multigate structures (trigate and FinFET), VT is de-
86 pendent on WSTRIPE since the side gates inﬂuence the channel
87 potential. Since the FinFET relies on narrow WSTRIPE to sup-
88 press SCE, it is much more sensitive to WSTRIPE variation than
89 the trigate bulk MOSFET design, which employs retrograde
90 channel doping to help suppress SCE, as shown in Fig. 4. Note
91	that the VT sensitivity to WSTRIPE is calculated at nominal		Fig. 2. Simulated MOSFET transfer characteristics (ID –VG). LG = 20 nm.
92	WSTRIPE with ±10% variation. The trigate bulk MOSFET		(a) tSi = 0.6 LG = 12 nm. (b) tSi = 0.8 LG = 16 nm.

93design with tSi = 0.8 LG exhibits the smallest (close to zero)

94VT sensitivity to WSTRIPE variations since the top gate constithe channel region in the trigate design, the amount of depletion 102

95 tutes a smaller portion of total gate area, as compared with the

96design with tSi = 0.6 LG.

97The effects of tox variation for tSi = 0.6 LG are shown in

98Fig. 5. The simulation results for tSi = 0.8 LG (not shown)

99show a similar trend. For the trigate and planar bulk MOSFET

100designs, VT increases (so that both IOFF and ION decrease)

101with increasing tox. Because the gate electrode wraps around

charge (due to ionized channel dopants) per unit channel width 103 is smaller than that for a planar bulk device; thus, the VT shift 104 induced by tox variation is smaller for the trigate design. The 105 SOI FinFET design shows different dependence, i.e., as tox 106 increases, IOFF increases due to worse electrostatic integrity, 107 and ION decreases due to worse subthreshold slope. This is 108 because the SOI FinFET structure relies on good gate control 109

SUN et al.: STUDY OF PLANAR MOSFET, SOI FinFET, AND TRIGATE MOSFET DESIGNS

Fig. 3. Simulated VT sensitivity to LG variation. LG = 20 nm. (a) tSi = 0.6 LG = 12 nm. (b) tSi = 0.8 LG = 16 nm.

IEEE

Fig. 4. Simulated VT sensitivity to WSTRIPE variation.

110 (i.e., a combination of ultrathin tox and narrow WSTRIPE) to

111suppress SCE, whereas the planar and trigate bulk designs both

112employ retrograde channel doping to help improve electrostatic

113integrity.

114Additional process-induced systematic variations such as

115that due to layout-dependent channel stress induced by a

116shallow-trench isolation (STI) oxide have become signiﬁcant

117for scaled CMOS technologies [10]. Fig. 6 compares STI-

118induced stress proﬁles and hole mobility variations for a planar

119bulk MOSFET versus a trigate bulk MOSFET. Since the surface

120of each channel stripe above the STI is elevated, mobility

121dependence on layout is dramatically reduced.

Fig. 5. Simulated ID −VG characteristics with tox variation. LG = 20 nm, and tSi = 0.6 LG = 12 nm. (a) Trigate bulk MOSFET design. (b) SOI FinFET design. (c) Planar bulk MOSFET design.

Stressors used to boost transistor performance are another 122 source of systematic variation; an example is the use of a 123 contact etch stop liner (CESL) for mobility enhancement. Fig. 7 124 shows the CESL-induced stress distributions along the channel 125 (current ﬂow) direction within the planar and trigate bulk 126 MOSFET structures. The narrow and geometrically regular 127 channel structure in the trigate bulk MOSFET results in more 128 channel stress (and thus more mobility enhancement) and less 129 variation in channel stress with changes in effective channel 130

width.

131

4 IEEE TRANSACTIONS ON ELECTRON DEVICES

		IEEE
Fig. 6.		Proof
	Comparison of (a) transverse stress proﬁles and (b) STI stress-induced hole mobility variations for planar versus trigate (WSTRIPE = 20 nm) bulk
MOSFETs using Taurus 3-D [11]. The silicon stripe height is 10 nm for the trigate bulk MOSFETs, which provides for more uniform channel mobility because
of reduced STI-induced channel stress.
Fig. 7.	CESL-induced stress distribution in planar and trigate bulk MOSFETs. The CESL is assumed to be a 30-nm-thick silicon nitride with 2-GPa tensile

stress. LG = 20 nm, tox = 9 Å, gate electrode thickness (TGATE) = 40 nm, spacer width (LSPACER) = 20 nm, WSTRIPE = 20 nm, WSPACING = 20, and HSTRIPE = 10 nm.

132IV. IMPACT OF RANDOM VARIATIONS

133Here, LERand RDF-induced variations are compared for

134the three MOSFET structures. Gate LER proﬁles are sampled

135from a scanning electron micrograph of extreme ultraviolet

136resist lines. On average, these lines have an LER (3σ) value

of 4 nm and a line width roughness (LWR) value of 6.4 nm. 137 The distance between the consecutive sampling points of the 138 LER proﬁles is approximately 0.8 nm. Examples of simulated 139 structures with different gate LER proﬁles are shown in Fig. 8. 140 The source and drain junction proﬁles are assumed to have 141

SUN et al.: STUDY OF PLANAR MOSFET, SOI FinFET, AND TRIGATE MOSFET DESIGNS

Fig. 10. LERand RDFinduced variations in trigate bulk MOSFET, SOI

Fig. 8. Examples of simulated gate electrodes with different LER proﬁles.	FinFET, and planar bulk MOSFET.	LG = 20 nm, and tSi = 0.6 LG =
	12 nm.

			IEEE
	Fig. 9. LER-induced variation in trigate bulk MOSFET, SOI FinFET, and
	planar bulk MOSFET. LG = 20 nm, and tSi = 0.6 LG = 12 nm.
142 the same LER as the gate electrode to simulate the worst case
143 scenario; thus, Le will have the same roughness proﬁle as
144	LG. The RDF proﬁles are generated using kinetic Monte Carlo
145 simulations [9] on the MOSFET structures with gate LER.
146	Three-dimensional device simulations are performed for the
147 optimized nominal designs to investigate the effects of LER
148 only and also to investigate the effects of LER, together with
149	RDF, in the source/drain and channel regions.
150	Fig. 9 shows the gate LER-induced VT variations (σVT )
151 for the SOI FinFET, planar bulk MOSFET, and trigate bulk
152	MOSFET with tSi = 0.6 LG. The variation is smallest for the
153 trigate bulk MOSFET design due to its superior electrostatic
154 integrity. The SOI FinFET has VT variation comparable to that
155 of the planar bulk MOSFET. This is because the two sidewall
156 gates of the FinFET have discrete different gate lengths due to				Fig. 11. Effect of tSi on LERand RDFinduced variations. LG = 20 nm.
157	gate LWR, whereas the effects of gate LWR on planar bulk
158	MOSFETs are somewhat averaged across the channel width.			(a) tSi = 0.6 LG = 12 nm. (b) tSi = 0.8 LG = 16 nm.
159	VT variations due to the presence of both LER and RDF are
160 shown in Fig. 10. VT lowering (where			VT is equal to the	gradient regions increases with smaller WSTRIPE [12] and 167
161	VT value of the nominal design subtracted by the mean VT			also because of larger LER-induced variation, the SOI FinFET 168
162 value of the MOSFET structures with gate LER and RDF)				does not provide for reduced random variation, as compared 169
163 is smallest for the trigate bulk MOSFET due to its superior				with the trigate bulk MOSFET design, although there are no 170
164 electrostatic integrity. Overall, the trigate bulk MOSFET also				channel dopants in the SOI FinFET. Fig. 11 shows the effect 171
165 shows comparable random VT		variation as the SOI FinFET.		of tSi on the random variation. For the trigate bulk MOSFET, 172
166	Because VT variation induced	by RDF	in the source/drain	tSi = 0.6 LG yields the smallest random variation, whereas 173

174 for the planar bulk MOSFET, tSi = 0.8 LG is beneﬁcial for 175 reduced RDF-induced variability since the average number of 176 channel dopants is smaller.

177	V. CONCLUSION

178The impact of process-induced systematic and random vari-

179ations on transistor performance has been investigated for three

180different transistor structures. As compared with the planar bulk

181MOSFET and SOI FinFET, the trigate bulk MOSFET design

182shows the least variability and the best nominal performance.

183Thus, it is a promising device architecture for transistor scaling

184to the end of the technology roadmap.

IEEE TRANSACTIONS ON ELECTRON DEVICES

[7] X. Sun and T.-J. King Liu, “Scale length assessment of the tri-gate 206 bulk MOSFET design,” IEEE Trans. Electron Devices, vol. 56, no. 11, 207

pp. 2840–2842, Nov. 2009.	208
[8] A. Hokazono, H. Itokawa, N. Kusunoki, I. Mizushima,	S. Inaba, 209

S. Kawanaka, and Y. Toyoshima, “Steep channel & halo proﬁles utilizing 210 boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond,” in VLSI 211

Symp. Tech. Dig., 2008, pp. 112–113.

212

[9] Synopsys, Inc., Mountain View, CA, Sentaurus User’s Manual, 2009.06, 213 2009. 214

[10]G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive 215 current reduction caused by transistor layout and trench isolation induced 216

stress,” in IEDM Tech. Dig., 1999, pp. 827–830.	217
[11] Taurus User’s Manual, Synopsys, Inc., Mountain View, CA.	218	AQ1

[12]V. Varadarajan, L. Smith, S. Balasubramanian, and T.-J. King Liu, “Multi219 gate FET design for tolerance to statistical dopant ﬂuctuations,” in 220

Proc. IEEE Silicon Nanoelectron. Workshop, 2006, pp. 137–138.

221

185

REFERENCES

Xin Sun, photograph and biography not available at the time of publication. 222

186[1] H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki, “Challenge:

187Variability characterization and modeling for 65to 90-nm process,” in

188		Proc. Custom Integr. Circuits Conf., 2005, pp. 593–599.		Victor Moroz, photograph and biography not available	at the time of 223
189	[2]	A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva,		Victor Moroz, photograph and biography not available	at the time of 223
189	[2]			publication.	224
				publication.	224
190			IEEE
190		“Simulation of intrinsic parameter ﬂuctuations in decananometer and
191		nanometer-scale MOSFETs,” IEEE Trans. Electron Devices, vol. 50,
192		no. 9, pp. 1837–1852, Sep. 2003.
193	[3] R.-H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: From			Nattapol Damrongplasit, photograph and biography not available at the time 225
194		bulk to SOI to bulk,” IEEE Trans. Electron Devices, vol. 39, no. 7,		of publication.	226
195		pp. 1704–1710, Jul. 1992.
196	[4] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling
197		theory for double-gate SOI MOSFETs,” IEEE Trans. Electron Devices,
198		vol. 40, no. 12, pp. 2326–2329, Dec. 1993.		Changhwan Shin, photograph and biography not available at the time of 227
199	[5]	D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for
				Proof
200		two-dimensional effects in MOSFETs,” IEEE Electron Device Lett.,		publication.	228
201		vol. 19, no. 10, pp. 385–387, Oct. 1998.
202	[6]	X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S. Ikeda,
203		C. Shin, and T.-J. King Liu, “Tri-gate bulk MOSFET design for CMOS		Tsu-Jae King Liu, photograph and biography not available at the time of 229
204		scaling to the end of the roadmap,” IEEE Electron Device Lett., vol. 29,
205		no. 5, pp. 491–493, May 2008.		publication.	230

AUTHOR QUERIES

AUTHOR PLEASE ANSWER ALL QUERIES

AQ1 = Please provide year of publication in Ref. [11].

END OF ALL QUERIES

IEEE

Proof

IEEE TRANSACTIONS ON ELECTRON DEVICES

1	Variation Study of the Planar Ground-Plane Bulk
2	MOSFET, SOI FinFET, and Trigate
3	Bulk MOSFET Designs
4	Xin Sun, Victor Moroz, Nattapol Damrongplasit, Changhwan Shin, and Tsu-Jae King Liu
5	Abstract—The impact of systematic and random variations
6 on transistor performance is investigated for the trigate bulk
7	MOSFET, the planar ground-plane bulk MOSFET, and SOI
8	FinFET. The results indicate that the trigate bulk MOSFET design
9 is least sensitive to process-induced variations and offers the best
10 nominal performance, as compared with the planar ground-plane
11	bulk MOSFET and SOI FinFET.
12	Index Terms—Fin-shaped FET, metal–oxide–semiconductor
13	ﬁeld-effect transistor (MOSFET), multigate FET, variability.
14	I. INTRODUCTION
15	ARIABILITY IN transistor performance dramatically in-
16	Vcreases as the critical dimension (the gate length) is
17	reduced well below 50 nm. This poses critical challenges for
18	continued CMOS scaling and cost-effective utilization of scaled
19	technologies [1]. Variations in transistor performance can be
20	divided into two main categories, i.e., systematic and random
21	variations. Sources of systematic variation include process-
22	induced variations in gate length LG, channel width WSTRIPE,		Fig. 1. (a) Three-dimensional view of MOSFET designs studied in this letter.
23	gate oxide thickness tox, and layout-dependent channel stress.		(b) Channel doping proﬁle for trigate and planar ground-plane bulk MOSFETs.
24	Sources of random variation include gate line edge roughness
25	(LER) and random dopant ﬂuctuations (RDF), which are also		(see Fig. 1(b), peaked at a depth tSi with 4-nm/dec doping 39
26	intrinsic sources of variation [2] (i.e., fundamental to the tran-		gradient [6], [8]) is used to improve the electrostatic integrity 40
27	sistor architecture and manufacturing processes).		[3], [6]. For the SOI FinFET, the channel is undoped.	41
28	As candidate structures to extend transistor scaling to its		Sentaurus 3-D device simulations [9] using advanced physi- 42
29	ultimate limit, the planar ground-plane bulk MOSFET, SOI		cal models are performed for the following n-channel MOSFET 43
30	FinFET, and trigate bulk MOSFET structures have been investi-		nominal designs: physical gate length LG = 20 nm, equivalent 44
31	gated [3]–[7]. A comparison of the scale lengths for these struc-		oxide thickness tox = 9 Å, and supply voltage VDD = 0.7 V. 45
32	tures shows that the trigate bulk MOSFET is more scalable than		Three-dimensional quantization effects are included using the 46
33	the other two designs [7]. In this paper, the impact of process-		density gradient quantization model. A hydrodynamic model 47
34	induced variations on transistor performance is investigated for		(ﬁt to Monte Carlo simulation results) is used to model carrier 48
35	each of these structures to see which one is most scalable.		transport [9]. For the trigate bulk MOSFET design, silicon 49
		IEEEstripe width WSTRIPE = LG and two cases of tSi (equal to 50
36	II. NOMINAL MOSFET DESIGNS		oxide recess depth HSTRIPE) are simulated (tSi = 0.6 LG 51
37	The transistor structures are illustrated in Fig. 1. For the pla-		and 0.8 LG) with the source/drain extension junction depth 52
38	nar and trigate bulk MOSFET designs, retrograde well doping		XJ = 1.2 HSTRIPE; for the planar bulk MOSFET design, 53
			same values of WSTRIPE and tSi are assumed, and XJ = 7 nm; 54
			for the SOI FinFET design, WSTRIPE is set to 0.6 LG to 55
	Manuscript received January 18, 2011; revised April 13, 2011 and June 24,		suppress short-channel effects (SCEs), and ﬁn height HSTRIPE 56
			is chosen to achieve the same effective channel width We 57
	2011; accepted June 28, 2011. The review of this paper was arranged by Editor
	S. Deleonibus.		as the Prooftrigate bulk MOSFET design. The trigate and FinFET 58
	X. Sun, N. Damrongplasit, C. Shin, and T.-J. K. Liu are with the Department		designs are assumed to have the same channel stripe pitch 59
	of Electrical Engineering and Computer Sciences, University of California,		(2 LG, which is an aggressive estimation), as this is set by 60
	Berkeley, CA 94720 USA (e-mail: sunxin@eecs.berkeley.edu).
	V. Moroz is with Synopsys, Inc., Mountain View, CA 94043 USA.		lithography limitations. For each design, the effective channel 61
	Color versions of one or more of the ﬁgures in this paper are available online		length (Le , which is modulated by offset spacer width) is 62
	at http://ieeexplore.ieee.org.
	Digital Object Identiﬁer 10.1109/TED.2011.2161479		optimized to minimize intrinsic delay Ctotal VDD/Ie , where 63

2 IEEE TRANSACTIONS ON ELECTRON DEVICES

TABLE I

OPTIMAL DESIGNS FOR THE TRIGATE BULK MOSFET, PLANAR BULK MOSFET, AND SOI FINFET

64	Ctotal is the total gate capacitance, and Ie is the average of
		IEEE
65 the drain current ID for VGS = VDD and VDS = VDD/2 and
66	ID for VGS = VDD/2 and VDS = VDD, at a ﬁxed 18-nA/μm
67 OFF-state leakage current IOFF, as speciﬁed for planar bulk
68	MOSFETs. The ID –VG characteristics of the optimal designs
69	(summarized in Table I) are shown in Fig. 2. The trigate bulk
70	MOSFET design with tSi = 0.6 LG shows the best subthresh-
71 old swing S due to superior gate control. It has 7% lower
72 intrinsic delay than the optimal SOI FinFET and 35% lower
73 intrinsic delay than the optimal planar bulk MOSFET design.
74	III. IMPACT OF SYSTEMATIC VARIATIONS
75	Here, the effects of systematic variations in LG, WSTRIPE
76	(for trigate and FinFET structures), tox, and channel stress
77 distribution (for trigate and planar MOSFETs) are discussed.
78	Fig. 3 shows threshold voltage (VT , which is deﬁned as
79 the voltage, where drain current ID is 100 nA We /LG)
80 sensitivity to LG variation. For tSi = 0.6 LG, VT variation in
81 the trigate bulk MOSFET design is the smallest among the three
82 structures. For tSi = 0.8 LG, however, it increases to the same
83 level as that of the planar bulk MOSFET design due to degraded
84 electrostatic integrity [7].
85	For the multigate structures (trigate and FinFET), VT is de-
86 pendent on WSTRIPE since the side gates inﬂuence the channel
87 potential. Since the FinFET relies on narrow WSTRIPE to sup-
88 press SCE, it is much more sensitive to WSTRIPE variation than
89 the trigate bulk MOSFET design, which employs retrograde
90 channel doping to help suppress SCE, as shown in Fig. 4. Note
91	that the VT sensitivity to WSTRIPE is calculated at nominal		Fig. 2. Simulated MOSFET transfer characteristics (ID –VG). LG = 20 nm.
92	WSTRIPE with ±10% variation. The trigate bulk MOSFET		(a) tSi = 0.6 LG = 12 nm. (b) tSi = 0.8 LG = 16 nm.

93design with tSi = 0.8 LG exhibits the smallest (close to zero)

94VT sensitivity to WSTRIPE variations since the top gate constithe channel region in the trigate design, the amount of depletion 102

95 tutes a smaller portion of total gate area, as compared with the

96design with tSi = 0.6 LG.

97The effects of tox variation for tSi = 0.6 LG are shown in

98Fig. 5. The simulation results for tSi = 0.8 LG (not shown)

99show a similar trend. For the trigate and planar bulk MOSFET

100designs, VT increases (so that both IOFF and ION decrease)

101with increasing tox. Because the gate electrode wraps around

SUN et al.: STUDY OF PLANAR MOSFET, SOI FinFET, AND TRIGATE MOSFET DESIGNS

Fig. 3. Simulated VT sensitivity to LG variation. LG = 20 nm. (a) tSi = 0.6 LG = 12 nm. (b) tSi = 0.8 LG = 16 nm.

IEEE

Fig. 4. Simulated VT sensitivity to WSTRIPE variation.

110 (i.e., a combination of ultrathin tox and narrow WSTRIPE) to

111suppress SCE, whereas the planar and trigate bulk designs both

112employ retrograde channel doping to help improve electrostatic

113integrity.

114Additional process-induced systematic variations such as

115that due to layout-dependent channel stress induced by a

116shallow-trench isolation (STI) oxide have become signiﬁcant

117for scaled CMOS technologies [10]. Fig. 6 compares STI-

118induced stress proﬁles and hole mobility variations for a planar

119bulk MOSFET versus a trigate bulk MOSFET. Since the surface

120of each channel stripe above the STI is elevated, mobility

121dependence on layout is dramatically reduced.

Fig. 5. Simulated ID −VG characteristics with tox variation. LG = 20 nm, and tSi = 0.6 LG = 12 nm. (a) Trigate bulk MOSFET design. (b) SOI FinFET design. (c) Planar bulk MOSFET design.

width.

131

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