Microscale addressing wires

Coded nanowires

© 2005 AAAS

of this work is that it combines the unique electronic properties of single-walled CNTs with controlled top-down lithography to pattern different work-function metals on the CNT so that both n-type and p-type regions can be realized as required for a CMOS device (Fig. 4c). Notably, in this five-stage device, which consists of five p-type and five n-type FETs, signal analysis showed resonances at up to 52 MHz that are consistent with stable oscillation of the device. This combination of strategies could be particularly advantageous for near-term nanoelectronic development, although ultimately hybrid approaches face many of the same constraints that limit conventional top-down processing used in industry today. Furthermore, the onedimensional nature of nanowires and nanotubes indicates that circuits are more easily built along the long axis of a single nanoscale wire.

This offers both design advantages and challenges: on the one hand, the nanowire or nanotube naturally serves as local interconnects and eliminates additional wiring; on the other hand, the success of these devices depends critically on the development of new architectures, including crossbar-motif logic architectures to take full advantage of the unparalleled material and structural control offered by the bottom-up approach.

Addressing nanoarrays

Addressing large numbers of memory bits inside a crossbar array will require demultiplexers (demuxes) that allow a relatively small number of control wires to access the large number of nanoscale

wires selectively inside the memory array. In an ideal demux, n pairs of microscale control wires can be used to select 2n nanowires; that is, 10 pairs of control wires can specifically address each of the 210 = 1,024 nanowires serving as the columns (or rows) of a 1 Mbit crossbar memory. By using a pair of demuxes serving respectively as row and column selectors, all 22n crosspoints (memory bits) inside the memory array can be selectively addressed by 2n pairs of control wires.

The first prototype crossbar demux was based on the transistor function of semiconductor nanowires20 in which control wires serve as gate electrodes that cross nanowires extending into and forming the columns or rows of the memory array. ‘Address coding’ of the nanowires inside the demux was obtained by surface modification during the ‘programming’ process at specific crosspoints to give them a lower threshold voltage VT than the unmodified ones15,20. The coded nanowire demux effectively forms a NOR plane: the nanowire will be turned off if any one of the control wires crossing it at the modified positions is in the high-voltage ‘1’ state.

Coding specific crosspoints through lithography, however, presents a significant manufacturing challenge for large demux arrays and limits the ultimate scaling advantage of assembled nanowire and CNT buildingblocks.Anintriguingapproachthatovercomesthislithography barrier involves stochastic demuxes formed using modulation-doped semiconductor nanowires. Threshold voltage modulation and hence address coding is obtained at the different crosspoints between gate wires and the nanowire channel, which may be either heavily or lightly doped (Fig. 5a)52. In this approach, the manufacturing cost of lithography and functionalizing specific crosspoints to obtain address coding is exchanged for that of creating modulation-doped nanowires during growth; that is, information is encoded during nanowire synthesis, not by lithography during circuit fabrication. Interestingly, this concept of coding during nanowire synthesis has many analogies with biology where the information is encoded during the synthesis of the linear sequence of bases in a replicated DNA molecule (Fig. 5a).

The stochastic demux scheme is particularly suitable for crossbars based on chemically grown nanowires, because the position registry is generally lost during the assembly using flow-alignment53 or Langmuir–Blodgett11 techniques, resulting in arrays of aligned albeit randomly positioned nanowires. Stochastic demultiplexing based on coded nanowires was recently demonstrated by Yang et al.54, where modulation doping along the nanowire axis was achieved with full control of the size, spacing and number of the modulated regions during the growth process (Fig. 5b). Crossed nanowire/microscale control wire demux arrays formed by randomly positioned codednanowires were shown to follow predictions52,54 (Fig. 5c), and thus demonstrate that it is possible to construct a unique demux that is independent of the constraints of lithography used in conventional top-down systems.

In electromechanical and resistive-switching crossbar memories, the memory bits are formed by hysteresis resistors or diodes14. By permanently setting specific crosspoints in these resistor arrays to the ‘closed’ state during the configuration process, wired-OR and AND logic (although with a reduced voltage margin) can be obtained by controlwirescrossingthesamenanowireattheclosedpoints.Usingthe wired-ORandANDlogic,rowandcolumndemuxesmaybebuiltusing mixed-scale crossbars consisting of nanowires leading to the memory array and microscale control wires from the CMOS circuitry. The crosspointsinthemixed-scalecrossbardemuxesneedtobeconfigured ‘permanently’ at manufacturing time or during configuration, and should not be affected by the write/erase operations of the memory array. This may require deposition of a different switching medium at the demuxes that shows larger switching threshold voltages compared with inside the memory array. Furthermore, linear resistor logic suffers from limited voltage margin: the voltage difference between the selected and non-selected nanowires may not be large enough to

Figure 6 Hybrid crossbar circuits. a, Hybrid crossbar/CMOS system based on the CMOL approach. Two sets of pins with different heights separately connect the row and column nanowires in the crossbar with the CMOS circuitry underneath. b, Schematic of the array-based system architecture. Each node in the array is a crossbar-based memory or logic device with its own address demux.

complete the specific write/erase function. To improve the voltage margin, several techniques have been proposed using CMOS coding to eliminate the worst-case scenarios41,55. However, considering the limited geometry and functions available in the crossbar resistorlogic, it is reasonable to expect workable demuxes to be in the form of hybrid resistor-crossbar/transistor structures in which the transistor circuitry provides the more difficult functions such as signal gain, restoration, inversion and impedance matching.

hybrid to nano Architectures

A hybrid crossbar/CMOS circuit takes advantage of both worlds: the ultra-high device density offered by the crossbar structure and the flexibility offered by the CMOS circuitry. But tradeoffs have to be made: larger crossbar proportion results in higher device density with greater circuit design and fabrication challenges, whereas larger CMOS proportion results in increased circuit functionality at a cost of increased chip area overhead. One hybrid crossbar/

© 2007 ACS

CMOS approach that has received considerable attention is the CMOS/nanowire/molecular hybrid (known as CMOL) structure21,22.

In the CMOL circuit (Fig. 6a), the CMOS-to-nanowire interface is provided by distributing two sets of via-pins uniformly over the whole circuit area. The two sets of pins have different heights so that the taller (shorter) set is connected to the top (bottom) nanowire electrodes in the crossbar array from the CMOS cells underneath. By rotating the crossbar at a small angle (determined by the relative pitch size of the crossbar and CMOS) with respect to the CMOS layer, each nanowire in the crossbar array can be connected to exactly one CMOS cell. In this approach, the most difficult functions — inversion, gain and demultiplexing — are moved into the CMOS layer, using the nanowires solely for data storage (in the case of memories), or wired-OR logic (in the case of logic circuits) and signal routing. A density advantage can still be maintained because only 2n CMOS cells are used to control n2 memory bits; however, the viability of processing on top of a high-performance CMOS structure on which considerable process development/cost has been expended needs to be further scrutinized.

Disregarding practical issues, preliminary studies have shown that CMOL memory with 32-nm CMOS technology could store 1 terabit of data in a 2 cm × 2 cm device22. In another hybrid crossbar/CMOS

proposal in which even more functions are shifted to CMOS circuitry and the crossbar is used only for data routing23, easier device fabrication and lower power dissipation are achieved at the cost of lower performance metrics including speed, density and defect-tolerance capabilities. Given these advances, the question seems to have shifted from whether hybrid cross/CMOS circuits are needed to how to implement these structures, and how to optimize the architecture by properly dividing functions between the two classes of components.

Once memory and logic devices (circuits) are implemented, array-based system architectures can be made by interconnecting the crossbar devices such that the output from one crossbar array forms the input of the other (Fig. 6b)8,21. The system architecture resembles the nano-architecture at the lower device level: It addresses a similar set of issues such as signal restoration and address demuxing, with the exception that each node in the array is now replaced by a functional memory or logic device. Moreover, the large connectivity of the 2D crossbar arrays provides the possibility to map neuromorphic networks onto distributed crossbar networks in a way that was not possible with CMOS-based approaches, with the potential to achieve artificial neural circuits with comparable density but orders-of-magnitude faster communication speed compared with the cerebral cortex56.