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Materials being investigated as potential candidates belong to the family of binary metal oxides such as (K = 10), (K = 20), (K = 25), (K = 23) and others.27 Introducing these high-K materials poses serious challenges to make the materials compatible with conventional CMOS processing. Other requirements are thermal stability and crystallization temperature, thermal expansion coefficient that matches that of silicon, low interface state traps at the dielectric-silicon surface, large energy bandgap and large silicon-dielectric energy barrier (see Figure 9.15b). The latter is important since the tunneling current is a strong function of the barrier height. These films suffer from a significant amount of traps and fixed charges that give rise to shifts in the flat band voltage, cause reliability problems, and degradation of the carrier mobility. Also, in many cases a thin interfacial layer is formed between the silicon substrate and the high-K material that increases the equivalent thickness of the dielectric,

Thus, the minimal achievable EOT will never be less than the interfacial oxide thickness. This poses a serious limitation on the maximum gate capacitance of a high-K dielectric. Processing of these materials poses equally challenging problems since compatibility with existing CMOS processing is important. They can be deposited by various means, such as metallo-organic chemical vapor deposition (MOCVD), atomic layer CVD (ALCVD), or sputtering. Transistors of 50 nm gate length with dielectric of 1.3 nm deposited with ALCVD have been demonstrated recently.28

9.7.4. Metal Gate Electrode

Current day transistors are fabricated with a highly doped poly-silicon gate. The advantage of poly-silicon is the value of its work function, high thermal stability, compatibility with high-temperature processing steps, and the self-aligned feature that reduces the overlap capacitance between the gate and the source/drain. However, a small depletion layer (about 0.5 nm) is formed in the poly-silicon material near the gate oxide interface. This causes a depletion capacitance that is in series with the gate oxide capacitance. For oxide thicknesses in the range of 1.5 nm, the depletion capacitance associated with the poly-silicon gate starts to become important and reduces the effect of the gate capacitance.25, 27 As a result, the coupling between the gate and the channel of the transistor is reduced. Another potential problem with the poly-silicon gate material is the high processing temperatures that are required. This can cause difficulties with the stability and integrity of the high-K gate dielectric. It is expected that poly-silicon gates will need to be phased out beyond the 65 nm technology node.2

A solution to the above problems is to replace the traditional poly-silicon gate with a metal gate. Since the carrier concentrations in a metal are much higher than in poly-silicon, the depletion layer is virtually non-existent. Metals can also be processed at considerably lower temperatures than poly-silicon. Among the criteria to select the proper metal material are the process compatibility, thermal stability, stability of the metal-dielectric interface and the work function. As discussed earlier, the work function influences the value of the threshold voltage (see Eq. 17). By selecting a material that has the proper work function, one can tailor the threshold voltage without having to rely on modifying the channel doping

level. This gives some leeway to optimize the channel doping in order to reduce shortchannel effects without compromising the threshold voltage. Ideally, one likes to have dual metal gates with work functions that are comparable to those of and poly-silicon.

Several candidate materials have been investigated—both single metal and alloys. One aspect that complicates the choice of metal is the fact that one likes to have a different work function of the NMOS and PMOS transistors in order to tailor the value of the threshold voltage for each. This would require two different materials or modifying a single metal gate. Dual metal gates have been used such as Titanium for NMOS and Molybdenum for PMOS transistors. Molybdenum has also been used as a metal gate whose work function has been modified by nitrogen implantation. Also, metal mixtures such as Ti-Ni and Ru-Ta have shown to be promising. By changing the metal mix one can adjust the work function to obtain the right value of the threshold voltages for the NMOS and the PMOS. These approaches are still under development and more research is needed to validate their success.

9.7.5. Cooled CMOS

Scaling has been the main factor driving up the performance of devices. However, the lack of full voltage scaling and the increased tunneling through the gate oxide will limit the amount of scaling of conventional bulk CMOS transistors to gate lengths of about 20 nm.29 One way to extend the devices beyond the 20 nm gate length is to cool them. At lower temperatures the scattering of the carriers is reduced resulting in higher mobility. In addition, the subthreshold slope S is proportional to kT/q, Lowering the temperature will give a steeper slope, which reduces the off-current considerably. This allows one to work with a lower threshold voltage and power supply. As a result, it may become feasible to extend the CMOS scaling down to the 10 nm regime.

9.7.6. Double-Gate MOSFET

Device scaling continues to pose more demanding constraints on the device design that makes optimization more and more difficult. As discussed above, one of the limitations of device scaling is the drain-induced barrier lowering, giving rise to reduced threshold voltage and increased leakage currents. By shielding the electric field of the drain from the source through the gate, the effect of drain-induced barrier lowering can be significantly reduced. This can be obtained with a smaller substrate depletion region and thus higher substrate doping levels. On the other hand, a small depletion region of the substrate reduces the coupling of the gate voltage to the channel potential and thus gives lower drive current, a larger body coefficient m and worse subthreshold slopes. These contradictory requirements on the substrate doping as a result of the need to reduce short channel effects and obtain good drive currents, pose serious limitations on the effectiveness of further scaling of conventional CMOS transistors.

The double-gate field effect transistor (DG FET) basically decouples these two requirements for the substrate doping.30,20 It has been predicted that the DG FET can be scaled

down to 50% of that of a bulk FET, making gate lengths of about 8–10 nm feasible for devices operating at room temperature.31 These predictions and recent successes with the fabrication of such devices make the DG FET a strong candidate to become the dominant device structure in the last era of CMOS scaling before one reaches atomic levels.32

A schematic cross-sectional representation of the DG FET is shown in Figure 9.25 together with a bulk MOSFET. A DG FET is a non-planar transistor with a top and bottom gate on both sides of a thin silicon channel. This allows one to control the potential of the channel much tighter than in the case of a conventional planar transistor where the effect of the substrate played a major role. The short-channel effects are now basically a function of the device geometry and not of the substrate doping. As a result, the substrate can be lightly doped or even undoped. The negligible depletion capacitance of the substrate allows for an effective coupling of the gate voltage to the channel potential which gives a steep subthreshold slope of about 60 mV/dec and a good drive current. This is an important advantage of the DG FET since it allows for a larger gate voltage over-drive and makes the DG FET particularly attractive for low power applications.

The low channel doping is also advantageous for the carrier mobility. However, it has been found that in a silicon channel thickness below 20 nm, the carrier mobility degrades when the inversion carrier density is low. For large inversion carrier densities (above ), which is usually the case in nanoscale CMOS, the degradation is much less pronounced. In addition, in undoped substrates the carrier transport is considerably better than in conventional devices. This is mainly due to the reduced scattering in the channel and the lower surface electric field. Both of these effects increase the

mobility in DG FET by a factor of about two as compared to that in conventional bulk FET.27

As can be seen from Figure 9.26, a DG FET can be fabricated with any of the three topologies shown.33 The type I structure most closely resembles the conventional planar bulk FET. It allows for uniform control of the channel thickness but poses difficulties to fabricate the bottom gate and a high quality gate dielectric. Also, making contact to the bottom gate is not easy and requires extra real estate which reduces the overall device density.

Type II and III DG FETs have their channel perpendicular to the substrate. Access to the top and bottom gates is easier than in the planar structure. On the other hand the substrate thickness is determined by lithographic techniques that make the uniformity control critical. For proper operation, the substrate (channel) thickness should be considerably smaller (3–4 ×) than the gate length, further complicating the dimensional control of the substrate for small length devices.

Type III structure has been most successful to date and is often called a FinFET.34, 35, 36 A schematic view of the FinFET is shown in Figure 9.27. The channel substrate sits on top of a silicon-on-insulator (SOI) substrate in the form of a fin. The thickness of the fin corresponds to the thickness of the silicon channel that needs to be tightly

controlled, using advanced patterning and etching techniques. A gate dielectric is grown or deposited on top of the fin before the poly-silicon gate is deposited on top of it, forming a saddle-like structure. The source and drain regions are adjacent to the fin. The distance between the source and drain regions determines the gate length while the height of the fin determines the gate width. In order to reap the advantages of the double gate structure, one must make sure that the parasitic overlap capacitances between the gate and source/drain regions are kept to a minimum. Process innovations will be necessary to reduce these and other parasitic effects, and to take full advantage of the reduced short channel effects and increased drive currents in these nanoscale devices.

The structures and materials discussed in this section will be needed to extend CMOS technology towards the end of the time horizon of the ITRS. Although no manufacturable solutions are known for several of the materials and structures discussed, it is believed that these materials and manufacturing challenges will be solved in order to keep the ITRS projections on track. The question that arises is, what will happen at the end of the roadmap? Will CMOS be replaced by more advanced technologies or will it co-exist with other, nonconventional technologies? The next section gives some insights to what lies beyond the traditional CMOS devices.

9.8. BEYOND TRADITIONAL CMOS

As discussed above‚ the technology roadmap (ITRS 2003) projects that transistors will have physical gate lengths of 8–9 nm by 2016. Initial experimental results obtained with non-traditional MOSFETs‚ such as the DG FET‚ indicate that the projections of the ITRS will most likely stay on its trajectory. However‚ manufacturing multi-billion-transistor circuits with nanoscale dimensions will become exceedingly difficult and expensive. These circuits will be extremely fast but will also consume a lot of power‚ requiring careful circuit design and choice of both highand lower-performance devices on the same chip to manage the excessive power dissipation. In addition‚ the dimensions of the devices are reaching molecular and atomic levels ushering us into a different regime dominated by quantum mechanical effects. Alternative technologies to CMOS need to be explored that will most probably become complementary to the existing CMOS technology. Among the candidate technologies are quantum devices‚ molecular electronics‚ organic (plastic) transistors‚ nano-

electromechanical structures (NEMS)‚ carbon nanotube transistors‚ and optical devices (see the next three Chapters).2‚37‚38

Figure 9.28 depicts the various technologies in a three-dimensional cube such as axes speed‚ size and cost. The energy per consumption is indicated by the intensity. Each

technology occupies a certain volume in this three-dimensional representation.2 Each volume is projected on the three planes in order to make it easier to determine the value of the three parameters for each technology. As can be seen for CMOS, the cost lies in the

are still in their infancy and lack experimental data. In that case, the data shown is based on assumptions and physical principles.2,37 Table 9.3 summarizes the parameters for the devices shown in Figure 9.28. and refer to the switching tie, and CD is the critical dimension.

It is interesting to notice that the applicability of several of the technologies shown in Figure 9.28 is application specific. As an example, Quantum computation provides an immense speed improvement for solving factoring algorithms such as encountered in encryption, turning an impossible computation into a practical one. However, quantum computers are not expected to be useful for general purpose computing.39 Quantum computing is in its infancy stage and devices that are suitable for realizing quantum computers are still under

investigation. One such promising device is called a spin-resonance transistor that consists of Si-Ge multilayers.40

Plastic or organic transistors are thin film transistors that are fabricated on plastic substrates instead of silicon. One application of organic electronics is the Organic Light Emitting Diodes or OLEDs. This technology offers the potential of very inexpensive electronics and displays that can be printed on flexible substrates. This opens up opportunities for new applications such as digitized newspapers, product labels, RF tags, printable electronics on clothing and other products. These applications do not require the high performance and densities of CMOS circuits but should be inexpensive and flexible.41 This technology is well advanced and several commercial products are being developed.42 The main disadvantages are the low speed (kHz) and large size (about of these devices.

Molecular electronics makes use of molecules that act as switching devices. The small size of these molecules would make it possible to build computers and memories of extraordinary density, a million times denser than today’s memories. Although the realization of molecular electronics is still far from reality, several groups have succeeded in developing molecules that act as electronic switches and memory. Simple nano-circuits built from molecular switches and wires are being developed.43 Of course, developing a circuit with a complexity similar to those of current day CMOS chips is still far away and many problems need to be overcome before the potential of molecular electronics can be realized.

Carbon Nanotube Field Effect Transistors (CNFET)

Carbon nanotubes are large‚ all carbon molecules which belong to the family of fullerenes. These tubes can be thought of as an expanded buckyball in which the midsection has been expanded to form cylinders. These tubes have diameters ranging from one to several nanometers and lengths of hundreds of micrometers. The carbon atoms in the tube contain no dangling bonds‚ making them extremely inert and stable. The tubes can be metallic or semiconducting depending on how the tube has been wrapped (see chapter on Carbon Nanotubes). Metallic nanotubes are very good electrical and thermal conductors‚ exceeding conductivity of copper. Semiconducting nanotubes are promising for the fabrication of high performance nanoscale transistors. Several research groups have fabricated carbon nanotube field effect transistors (CNFET). The advantage of these transistors is that their structure is very similar to silicon based field effect transistors and do not need a completely new fabrication technology.44

IBM recently announced a high performance single carbon nanotube transistor that was fabricated with standard CMOS technology.45 A schematic cross section of a CNFET based on the conventional MOSFET structure is shown in Figure 9.29. The transistor has a top gate similar to a MOSFET. The carbon nanotube of only 1.4 nm in diameter has been carefully deposited by spinning the tubes from a solution of decholoroethane (1.2 M) on top of a silicon oxide layer. Titanium source and drain electrodes were patterned. By annealing the structure‚ good contact between the titanium and nanotube was obtained through a thin titanium-carbide interfacial layer. A gate oxide of 15 nm was deposited at 300°C on top of the tube. A top electrode consisting of titanium or aluminum was deposited.

The mechanisms of the CNFET operation are not fully understood yet but recent results have indicated that CNFET operate as Schottky barrier transistors rather than conventional bulk transistors. This implies that one does not need to dope the carbon nanotubes. By

modifying the barrier height one can obtain n-type and p-type devices‚ making it feasible to fabricate CMOS devices based on carbon nanotubes.

The CNET has a steep subthreshold slope and a transconductance which are better than that found in silicon transistors. Also‚ the speed of the electrons along the tubes is considerably better than in silicon due to the ballistic transport. Carbon nanotubes can be packed as close as 3 nm apart‚ giving rise to extraordinary densely packed devices. Among the improvements that are needed are thinner gate oxide of about 1.5 nm‚ and shorter gate lengths in the range of a few nanometers. It is expected that these changes will give a few orders of magnitude improvements in performance. The current results and the further improvements in performance are very promising and give a glimpse of how high performance nanoelectronic circuits may be fabricated in the post ITRS roadmap era.

These and other emerging technologies are discussed in different chapters in this book. We expect that these technologies will co-exist with CMOS technologies in a hybrid fashion. They will enhance microelectronics by adding functionality. Systems consisting of various subsystems manufactured with different technologies will offer the most economical and reliable solution. Information processing systems will not be limited to electronic systems but will include microfluidics‚ biosensors and systems on a chip‚ and other complex information processing systems that go beyond conventional CMOS systems.

9.9. SUMMARY

Microelectronics is one of the most sophisticated manufacturing methods devised by mankind.

CMOS is the dominant technology.

The transistor count and functionality per chip have doubled every 18 months for the last 40 years (Moore’s law).

Scaling of device dimensions has allowed the microelectronics industry to stay on the trajectory of Moore’s law.

Feature size reduction of 30% every 2 to 3 years. Generalized scaling laws most popular in industry Improved performance: 30% speed increase per year. Reduced cost per function: 25–32% per year.

Devices are entering the nanoscale. Scaling is expected to continue until physical transistor gate lengths of about 8–10 nm are obtained.

Limits of scaling:

Subthreshold current (off-current) does not scale.

Hot electrons and tunneling in the small-dimension transistors can become excessive.

Doping fluctuations cause large threshold voltage variations.

Power density as a result of the leakage current increases more rapidly. than the active power and will be one of the major limitations to scaling.

Improved device structures and materials are required to continue the scaling for the next decade. Promising approaches are:

Silicon on insulator Strained silicon

Double gate FET

Hi-K gate materials replace the traditional

Metal gate electrodes will replace the traditional poly-Si gate. Approaches beyond the conventional CMOS transistors:

Plastic electronics Molecular electronics Quantum electronics Carbon Nanotubes

It is expected that these non-conventional technologies will not replace CMOS silicon but will co-exist.

CMOS will form a substrate and be integrated with non-traditional devices Silicon technology will form the basis for new nanoscale structures

Powerful systems on a chip (SoC) consisting of various technologies such as nanoscale microelectronics‚ microfluidics‚ biosensors‚ novel nano-devices and complex information processing systems will emerge.

QUESTIONS

1.Consider a p-type Silicon wafer with a resistivity of Assume that the hole and electron mobility in bulk silicon at 300 K is and respectively.

a.What is the doping concentration of the acceptor atoms in the bulk silicon?

b.What is the concentration of minority carriers in the bulk?

c.Calculate the Fermi voltage of the bulk silicon at room temperature.

d.At what temperature will the intrinsic carrier concentration be equal to the doping level?

a.Calculate the equivalent oxide thickness EOT and the dielectric capacitance per unit area.

b.What is the maximum width of the depletion layer when the surface is inverted?

c.Calculate the flat band voltage assuming that no ion implantation has been performed to adjust the threshold voltage.

d.Calculate the value of the threshold voltage

e.Assume that one needs a threshold voltage of 0.65 V. What is the implantation dose needed to adjust the threshold voltage? Do you implant donors or acceptors?

3.Consider the following modified MOS capacitor (gated diode). The capacitor has the same parameters as in problem 2. Explain qualitatively how the following parameters will be affected: and

4.A NMOS transistor is fabrication on a silicon substrate with doping level The oxide thickness is 6 nm and the threshold voltage at room temperature is equal to

0.45 V.

a.Calculate the body effect coefficient m and the subthreshold slopes of the NMOS and PMOS transistors at 300 K‚ 375 K and 77 K. Assume that the contribution of the interface states to the body effect coefficient is 0.15.

b.Calculate the leakage current in the NMOS at 300 K‚ 375 K and 77 K when for a transistor with a W/L = 10. Assume that the mobility of the electrons at the respective temperatures is equal to: 500‚ 300‚ respectively. The threshold voltage temperature coefficient is —0.8 mV/°C.

c.Also calculate the current in saturation for for the three temperatures.

d.In order to keep the leakage current at 77 K the same as at 300 K‚ how much smaller can one make the threshold voltage? Give the value of the threshold voltage at 77 K and 300 K.

e.In order to keep the current in saturation at 77 K the same as at room temperature‚ how can one reduce the power supply at 77 K?. Assume that the at room temperature is 2 V.

5.Assume an oxide thickness and a depletion layer thickness in the poly-silicon gate of

a.What is the combined capacitance of the oxide and poly-silicon depletion layer?

b.Assume that you need to keep the contribution of the poly-silicon depletion capacitor to the effective oxide less than 10% of the oxide capacitance. What is the maximum depletion thickness of the poly-silicon layer one can tolerate?

6.Using the rules of constant field scaling‚ prove that the scaling of the transistor current I‚ the delay and power dissipation behave as given in Table 9.1.

7.Using the rules of constant voltage scaling‚ prove that the scaling of the transistor current I‚ delay and power dissipation behave as given in Table 9.1.

8.Using the rules of constant-field scaling‚ find the scaling rule for the subthreshold leakage current.

9.The scaling rules given in Table 9.1 assume that the transistor does not suffer from velocity saturation. What would the scaling rules be for the current‚ delay and power dissipation in case of velocity saturation and generalized scaling?

10.The transit time in a transistor is defined as the ratio in which Q is the charge in the inversion region.

a.Find the expression of the transit time assuming that the transistor is operating in the linear region. How does the transit time scale for constant voltage scaling?

b.Find the expression of the transit time when the transistor is operating in the saturation region. You can assume a long channel transistor. The expression of the charge Q in the channel is two-thirds of the charge when the transistor is in the linear region.

11.Consider the following gate dielectric:

a.A dielectric layer has a K-value of 16. What is the thickness of the layer in order to obtain

an EOT of 1 nm? Assume that the K value of is 3.9.

b.The dielectric stack consists of a 0.5 nm interfacial layer. What is the thickness required of the high-K layer in order to obtain an overall EOT of 1 nm? Assume that the high-K material has a K value of 16.