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assume that the voltage scales with the same factor as the dimensions. We call this constantfield scaling. According to the expression (9.13) of the doping level should increase by a factorto keep the depletion width constant, assuming that the voltage scales with the same factor. We can now find the effects of scaling on the current, propagation delay and the power consumption. The current will reduce by the factor according to Eq. (9.24). The capacitance will also decrease by the same factor. This implies that the delay, which is proportional to CV/I, will be reduced by a factor The total power consumption, which is proportional to the product of current and voltage, will decrease by a factor of On the other hand, the power per unit area will remain constant. The result of the device scaling is given in the Table 9.1.

An alternative scaling method is constant-voltage scaling where the voltage is kept constant. The advantage of constant-voltage scaling is reduced circuit delay, which scales with the square of the scaling factor. The main drawback is the large electric fields that can cause reliability problems for the devices. In reality, one often takes an approach between constant voltage and constant field scaling, called generalized scaling. This is done to optimize the speed, power dissipation and device reliability. The scaling rules for the different scaling approaches are given in Table 9.1, assuming that the transistor does not suffer from velocity saturation and operates in strong inversion.

The scaling trend of the nominal feature size and physical gate length of transistors in high-performance circuits is shown in Figure 9.4. As can be seen from the figure, the scaling of the transistor’s gate length has become more aggressive since the middle of 1990’s than that of the features used in DRAMs, indicating that microprocessors have been driving the technology. Figure 9.19a illustrates the scaling trends of the delay, power density and current drive per unit gate width as found in industry, as well as the trend predicted by constant field scaling (dashed lines).18 The delay follows nearly the constant field scaling law but the power density has increased significantly faster, mainly because the power supply has not been scaled with the same factor as the gate length. Also, the current drive has increased more than predicted by the constant field scaling, while the gate capacitance has decreased more than predicted. This is due in part to the fact that the gate length has scaled more aggressively than the oxide thickness and also due to the subscaling of the power supply.

With the rise of mobile computing applications and the increased integration density, the need for low power devices and power efficient circuit design has grown considerably. Table 9.1 illustrates that the power density increases as for constant voltage scaling and as for the generalized scaling method. This problem is highlighted in high performance microprocessors that consume up to about 100 Watt.19 If the trend in scaling continues, the power consumption of microprocessors is going to become excessively large, approaching power densities comparable to those found in a nuclear reactor! Clearly, power dissipation is going to become a major limitation that needs to be addressed. Reducing both the active power and the subthreshold power dissipation by improving the technology, lowering the power supply aggressively, dynamically adjusting the threshold voltage, switching off part of the circuits when not in use, new device structures, more efficient architectures, etc., are becoming hot research topics.

9.6. SMALL-DIMENSION EFFECTS

The goal of scaling is to adjust the device dimensions in such a way that the transistor characteristics will remain basically the same as the long channel devices. Although scaling has provided a successful method to reduce the device dimensions without decreasing its performance or reliability, some parameters do not scale well which has caused specific problems associated with small-dimension transistors. These include increased off-current, short-channel and narrow-width effects, increased current density and hot electrons.16

9.6.1. Scaling of the Subthreshold Current

When one switches a transistor off by making the gate voltage the transistor is not completely off but will be in the subthreshold regime. A certain amount of off-current will flow, as is given by the expression (9.29) with Since the capacitance increases with scaling, the off-current or the subthreshold leakage current also increases with scaling. In addition, the exponential dependency of the leakage current on the threshold voltage has caused the power density associated with the subthreshold current to increase exponentially with scaling. In order to limit this increase in power dissipation, one has reduced the threshold voltage to a lesser extent than is prescribed by the constant field scaling. Nevertheless, according to industry trends, the subthreshold power density has increased much faster than the active power density. Unless this trend changes, the subthreshold power density will become equal to the active power for a gate length of about 20 nm, as illustrated in Figure 9.19b. The situation gets even worse at higher temperatures since the subthreshold current increases faster with temperature than does the active power dissipation. Techniques such as using two threshold voltage levels, or biasing the substrate to reduce or increase the threshold voltage (through the body effect) are being applied to overcome the tradeoffs between leakage current and delay, active and passive power dissipation. For low power applications, one often has to sacrifice performance by selecting processes with a higher and thus lower off-currents.

9.6.2. Hot Electrons

Due to the lack of scaling of the subthreshold current, constant electric field scaling is not feasible for high performance circuits. Thus, the electric field across the channel in small dimension transistors increases significantly over long channel transistors. An electron that travels from the source to the drain can gain enough kinetic energy and move into higher energy levels in the conduction band. Such electrons are called “hot” electrons. A few of these electrons will have gained enough energy to overcome the energy barrier (E = 3.1 eV) between the silicon and the oxide (Figure 9.15). The majority of these electrons will be collected at the gate electrode but some of them will be trapped inside the oxide. These charges contribute to the effective oxide charge and will increase the threshold voltage Also, the amount of interface states will increase due to the damage caused at the interface, increasing the body-effect parameter m and the subthreshold slope S. Careful design of the device parameters and the use of a lightly doped drain (LDD) help alleviate this problem.

9.6.3. Short-Channel Effects and Drain-Induced Barrier Lowering

For short channel transistors, the charge in the depletion region is shared between the source/drain and the gate. As a result, the amount of depletion charge that determines the threshold voltage is reduced for short length transistors, causing a roll-off of the threshold voltage with decreasing gate length. Figure 9.20 illustrates that the depletion region under the gate is in part determined by the voltage of the drain and source terminals.

When the gate length becomes very small as compared to the source and drain junction depth and the depletion width, the gate may not be able to fully control the potential in the channel region. The drain voltage will influence the voltage in the channel near the

source. This is called Drain-Induced barrier lowering (DIBL). This results in a reduction of the threshold voltage, an increase in the subthreshold current with drain voltage, and in punch-through between the source and drain. The latter gives rise to a large leakage current independent of the gate voltage. Minimizing the distance between the channel region and the quasi-neutral bulk can reduce the DIBL effect. This requires a small substrate depletion width (and high channel doping), shallow source and drain junctions, or a non-uniform channel implant in the lateral and vertical direction (superhalo implant). DIBL is one of the major limitations to scaling of conventional planar FETs.

9.6.4. Narrow-Width Effects

For narrow width channels the depletion width under the gate will extend along the width direction of the channel. This causes an increase of the threshold voltage since the total charge in the depletion region has increased (Eq. 17). As was the case for the short channel effect, the narrow width effect can also be reduced by a smaller depletion region width (or higher substrate doping). On the other hand higher substrate doping levels degrades the mobility of the carriers in the inversion layer. Careful engineering of the substrate doping profile has become essential to ensure proper operation of the scaled devices.

9.6.5. Velocity Saturation

The velocity of the mobile carriers increases proportionally with the electric field. However, when the field gets large ( for electrons), the carriers lose their energy quickly and the mobility decreases. The drift velocity of the carriers reaches a maximum value for electrons and for holes in the channel region. This phenomenon is called velocity saturation. In short channel devices, velocity saturation can occur due to the large electric field. As a result, the current will not increase with the drain voltage anymore and be independent of the channel length L. The current for very short channel devices then becomes equal to,

This has an effect on the scaling behavior of the transistor since the current is independent of the gate length and linearly dependent on The scaling factor for the

generalized scaling of the current in the velocity-saturation regime is equal to instead of (Table 9.1).

9.6.6. Source-Drain Resistance

Scaling of the device dimensions also includes the junction depths. This causes the sheet resistance of the source and drain to increase. This resistance gives rise to a voltage drop that reduces the available voltage between the gate and the internal source terminal. This parasitic series resistance can give a considerable current reduction in short channel transistors. Techniques such as an amorphization implant for shallow junctions or laser annealing of the junctions will become important to obtain low sheet resistance in shallow junction.

9.6.7. Doping Fluctuations

For small dimension transistors the amount of dopants in the channel region that controls the threshold voltage becomes very small. The randomness in the number and location of these dopants will give rise to significant variations in the threshold voltage from device to device.20 As an example, a transistor with a gate length of 100 nm and width of 400 nm has about 1000 dopants in its depletion region. When the gate length is reduced to 25 nm, the number of dopants decreases to about 120. The number fluctuation from device to device is given by the standard deviation that is equal to the square root of the number of dopants. For a 25 nm gate length this amounts to about 11 out of 120 dopants, which is a very significant fluctuation. This has a direct impact on the threshold voltage variations from device to device since the number of ionized dopants determines the value of the threshold voltage. These variations can be reduced by carefully tailoring the doping profile in the channel region, such as in a retrograde-doped channel. A retrograde-doped channel consists of a low-high doping profile. Doping fluctuations are now moved away from the channel to reduce their effect on the threshold voltage.

Transistors with a 15 nm physical gate length have been demonstrated recently.3,4 These transistor dimensions are well ahead of the ITRS target (Figure 9.21). One paper describes a transistor that was fabricated with a 1.4 nm (0.8 nm effective oxide) thickness nitride/oxinitride gate dielectric stack with a poly-silicon gate electrode, with ultra-shallow source/drain junctions, and compact halo profiles in the channel region to reduce shortchannel effects. The NMOS and PMOS devices obtained gate delays (CV/I) as small as 0.29 ps and 0.68 ps, respectively, at a supply voltage of 0.8 V. This illustrates that planar CMOS technology has the potential to stay the mainstream technology for the next decade. However, continued efforts will be needed to overcome the device design and process barriers to meet the ITRS target.

9.7. NANOSCALE MOSFET TRANSISTORS: EXTENDING CLASSICAL CMOS TRANSISTORS

Transistor dimensions have been reduced by about 30% every 2–3 years, allowing the semiconductor industry to follow Moore’s Law which states that the number of functions per chip doubles every 18 months. According to the International Technology Roadmap of the

Semiconductor Industry Association, downscaling will continue in the foreseeable future, with the printed and physical gate lengths of transistors reaching 13 and 9 nm, respectively, by 2016.2 The following table gives some of the key requirements and parameters, projected for the next 15 years. The technology node in the table refers to the dimension of the halfpitch of a DRAM cell that has historically been the technology driver. However, since the 90’s the technology to manufacture high-performance microprocessors (MPUs) has accelerated and is currently driving the most advanced processes. The gate length of transistors used in microprocessors has dimensions that are considerably smaller than the DRAM half-pitch, as can be seen in Table 9.2.

The transistor physical gate lengths will decrease from 45 nm in today's advanced processes to about 9 nm in the next decade. Figure 9.21 illustrates this trend for the physical and printed gate length of transistors used in MPUs. As can be seen, the gate length has decreased by a factor of 0.7 every 2 years over the past 5 years, which is faster than what was originally projected. It is anticipated that this acceleration will continue until about 2005 after which the scaling will be done on a 3-year cycle instead of a 2-year cycle. As a result of the aggressive scaling, the small-dimension effects discussed in the previous section will become more pronounced and the limits imposed by the physics and the materials will pose serious challenges. The traditional solutions involving complex doping profiles of the channel and drain/source regions will become inadequate to keep the small-dimension effects from degrading the transistor performance.

As discussed earlier, among the main challenges posed by the limits of scaling are short channel effects, the thin gate oxides, in particular the leakage currents including the gate leakage due to quantum-mechanical tunneling, the subthreshold leakage, junction leakage, band-to-band tunneling between the reverse biased drain and the highly doped substrate, and direct tunneling between the source and drain through the channel potential barrier. Replacing the traditional insulator by alternative materials with high K dielectrics will be required to reduce some of the leakage problems. Since subthreshold leakage current is

not suppressed by introducing new materials, it is going to be one of the ultimate limitations to scaling. This implies that the limits to scaling are going to be application dependent, with low power applications imposing stricter limitations on leakage currents than highperformance applications.

In addition, the polysilicon gate electrode has the limitation associated with the depletion region and boron out-diffusion, reducing the beneficial effects of device scaling. As a result, new metal gate materials will be needed in conjunction with the high K dielectrics. Innovations in both the device structures and the materials will ensure high-performance operation of nanoscale electronic devices. Some of the more promising approaches are discussed below.

9.7.1. Silicon on Insulator (SOI)

The conventional way to fabricate CMOS circuits has been on bulk silicon wafers as discussed above. The need for continued improvement in performance of scaled transistors has put considerable constraints on the devices, such as low parasitic capacitances and reduced threshold voltage, in order to obtain good drive current. On the other hand the requirement for low power operation demands low off-currents and thus a large threshold voltage. Fulfilling these contradictory requirements becomes more and more difficult in conventional bulk CMOS. Silicon on insulator (SOI) technology provides an attractive alternative since SOI CMOS transistors have minimal junction capacitance, they have no body effect, do not suffer from latch-up, and have a good subthreshold slope. This makes SOI particularly attractive for low-power applications and radiation hard circuits.

SOI CMOS transistors are built on a thin layer of single crystal silicon that is separated from the substrate by a silicon dioxide film, as schematically shown in Fig. 22. There are two main methods to obtain the SOI wafer. In the first method, oxygen atoms are implanted beneath the silicon surface at about 500°C to form a buried oxide (SIMOX—Separation by

IMplantation of OXygen) of about 400 nm thickness. The other method, called SOITEC, makes use an oxidized wafer implanted with hydrogen atoms at a certain depth and a second wafer that is bonded to the first one. After heating, the two wafers split at the place of high hydrogen concentration, leaving a thin layer of crystalline silicon on top of the oxide.

The SOI devices can be grouped into two categories, depending on the thickness of the silicon layer and doping level. For very thin silicon layers, the depletion width underneath the channel of the transistor is usually larger than the silicon thickness, giving rise to a fully depleted (FD SOI) transistor. The partially depleted (PD) SOI transistor makes use of a thicker silicon layer and has a quasi-neutral substrate region.

9.7.1.1.Partially Depleted SOI When the silicon layer is thicker than the maximum gate depletion width, the transistor is called partially depleted. The PD SOI is currently the most used SOI technology since the processing is similar to that of bulk CMOS, with the additional advantages of low junction capacitance and the lack of body effect. However, PD CMOS poses a problem as a result of a floating-body. This leads to the charging of the body due to the generation of carriers by impact ionization in the drain region. These carriers

are stored in the floating substrate and will change body potential and thus the threshold voltage.21 Also, the source-substrate junction can become forward biased causing larger

leakage currents. Using a substrate contact can reduce this effect at the expense of larger area and the loss of the body-effect advantage in SOI. In many cases, circuits fabricated in PD SOI technology need to be redesigned in order to reduce the detrimental effects of the

floating body. When done properly, PD SOI is an attractive alternative over bulk CMOS for low-voltage and low-power CMOS circuits.22

9.7.1.2.Fully Depleted SOI In a fully depleted CMOS transistor the subthreshold slope can be near ideal since the body effect coefficient m (see Eq. 22) is almost equal to 1. This is because the effective depletion width can be considered to be very large. A steep subthreshold slope allows one to use a lower threshold voltage for the same leakage current and thus lower supply voltages. However, a thick buried oxide reduces the beneficial effects

of PD SOI for short channel transistors. This is because the drain-source field penetrates through the oxide and thus results in poor short channel effects.23 It has been reported that by

using an ultra-thin silicon film of 2 nm and a local buried oxide of 20 nm, the short channel effects can be suppressed in devices with channel lengths of 20 nm.24 The unique feature

of this approach is that the buried oxide is not continuous as in the other SOI approaches but is limited to the gate regions. This has the advantage of SOI combined with the deep

source/drain regions giving rise to reduced series resistance of the source and drain. The silicon film and the buried oxide are defined by epitaxy on a bulk substrate and can thus be very accurately controlled, allowing the growth of very thin and uniform layers. These thin layers suppress the short channel effects and drain induced barrier lowering effects (DIBL). It is expected that PD SOI will become the dominating technology in the near future for CMOS for the 50 to 30 nm nodes.

9.7.2. Strain (Silicon-Germanium)

As mentioned in section 9.3.3, the mobility of the carriers increases significantly in strained silicon. Transistors built on strained-silicon wafers have shown mobility improvements up to 110% in NMOS and 45% in PMOS transistors.15 The strained silicon is obtained by growing an epitaxial silicon layer on top of a silicon-germanium layer (Figure 9.23). When the larger germanium atoms replace the silicon atoms, the distance between the silicon-germanium atoms is larger than in a pure silicon crystal. The change in the crystal geometry reduces the scattering and decreases the effective mass of the carriers. This technology has the advantage that the conventional device structure can be maintained. A drawback is the increased junction leakage and junction capacitance (source and drain to substrate diodes) due to the energy gap in SiGe layer being smaller and the dielectric constant being larger than that of silicon. To eliminate the excessive leakage and junction capacitance, silicon on insulator (SOI) wafers will be used for the silicon-germanium process.25

9.7.3. Hi-K Gate Dielectrics

Reducing the thickness of the gate dielectric is important in order to reap the advances of scaling in terms of reduced device delays (CV/I). Indeed, scaling the thickness is necessary not only to obtain a large transistor drive current, but to also reduce the short-channel effects as discussed earlier. The gate oxide thickness in state-of-the art devices for highperformance applications (e.g., microprocessors) is currently in the range of 1–1.5 nm and it is projected that the equivalent oxide thickness will be reduced to 0.4–0.5 nm by 2016

(Figure 9.24 or Table 9.2). The thickness will have been reduced to only a few atomic layers which causes large gate leakage currents due to direct tunneling through the oxide. Leakage current densities for a 1.5 nm thick is about at 1 V. Since the main leakage mechanism through these thin layers is direct tunneling of electrons, the leakage current is an exponential function of the layer thickness. Reducing the oxide thickness to 1 nm would increase the leakage current to at 1 V.26 For high performance applications it is generally assumed that a silicon oxide can be used down to a thickness as small as 0.8 nm.20 Also, oxinitride, nitride films or a nitride/oxinitride stack will be near-term solutions for high performance devices. However, for low power applications where smaller leakage currents are required, silicon oxide films below 1.5 nm will give excessive leakage currents and alternative materials will be required as soon as the 80 nm node (Table 9.2).2

One solution for the increased leakage current is to replace the traditional dielectric layer with a material that has a larger dielectric constant K than that of silicon oxide. This allows one to use a layer that has a larger physical thickness while maintaining a smaller equivalent physical thickness (or EOT),

in which (=3.9) is the dielectric constant of and is the dielectric constant of the actual gate dielectric. One notices that by using a high-K material, one obtains a small equivalent oxide thickness even if the actual physical thickness is considerably larger.