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to break away and move freely inside the silicon crystal, giving rise to conduction. In the energy band model of Figure 9.13a, the energy level of the valence electron associated with the phosphorous atom is very near the energy of the bottom of the conduction band As a result, the electron will jump into the conduction band leaving behind a fixed positive phosphorous ion.

At room temperature, each added phosphorous atom will donate one mobile electron. For that reason we call the phosphorous atoms donors. The concentration of the mobile electron concentration n will be equal to the sum of the concentration of the donor atoms

and the intrinsic concentration

A typical doping concentration is or higher so that at room temperature, Notice that the hole concentration is no longer equal to the electron concentration since the donor only contributes a free electron and no hole, resulting in a larger electron concentration than hole concentration, n > p. We call this an n-type semiconductor in which electrons are called majority carriers and holes are called minority carriers. Other atoms, such as As (arsenic) and Sb (antimony) can be used as donors.

By doping silicon with an atom from column III in the periodic table, such as boron, we can obtain p-type silicon. Since boron has only three valence electrons it will try to capture one electron so that the silicon atoms have 8 electrons to fill its outer shell. This results in the generation of a free hole, as schematically illustrated in Figure 9.14.

Each boron atom contributes an energy level close to the top of the valence band This allows an electron to jump easily from the valence band to the acceptor level, leaving behind a free hole and creating a negative B ion. Since boron accepts an electron, we call them acceptors. At room temperature, all the acceptor energy levels will be filled with electrons from the valence band, contributing a number of holes equal to the number of acceptors. As a result, at room temperature the hole concentration p will be equal to

For typical acceptor concentration used in semiconductors at room temperature making As will be seen later on, the product of the electron and hole concentration np at equilibrium is equal to,

So far we have qualitatively described that a certain amount of electrons will jump across the bandgap and fill up states in the conduction band, leaving states empty in the valence band, giving rise to mobile electrons and holes. In order to quantitatively describe the number of electronics or holes, we introduce an important function called the Fermi function F(E). The Fermi function gives the probability that an energy state E will be occupied by an electron. Assuming discrete energy levels in which Paul’s exclusion principle allows only two electrons per energy level, the function F(E) is given by,

in which is the Fermi level that is defined as the energy level at which the probability of finding an electron is equal to 0.5. Notice that when E is much larger than the Fermi energy the function and when E is much smaller than the function Assuming that we know the density of states N(E) in the conduction and valence bands, we can then use the Fermi function to calculate the concentration of the electron and holes in the semiconductor.13 When the energy E of the state is a few times kT larger than the Fermi energy the function F(E) can be approximated as,

We call this the Boltzmann approximation. This allows us to write the electron and hole concentration as follows.

in which and are the effective densities of states in the conduction and valence bands, respectively, and is the intrinsic energy level corresponding to the Fermi level in an intrinsic semiconductor. From Eqs. (9.8) and (9.9) one can easily prove that the product For n-type semiconductors the Fermi level will lie above the middle of the energy band gap and for p-type semiconductor will lie in the bottom half of the band gap.

The conductivity of the semiconductor can be expressed as a function of the electron and hole concentrations and carrier mobility.

in which is the resistivity, q the electron charge, and and the electron and hole mobility, respectively. By adding dopants one can change the conduction over a very large range. This is a key property of semiconductors that will become important for the operation of semiconductor devices as discussed later on. The mobility of the electrons is typically 2–2.5 times higher than that of the holes. This will imply that devices in which electrons cause the current will be faster than devices in which holes are responsible for the current flow. The mobility is a function of both doping levels and temperature. The higher the temperature and doping concentration, the lower the mobility will become due to increased scattering of the charge carriers with the atoms.

An interesting aspect is the effect of elastic strain on the mobility of mobile charges.14 This phenomenon has recently been used to improve the performance of field-effect transistors. By implanting germanium in the silicon, the lattice of the alloy will expand in the plane of the surface as compared to that of the pure silicon crystal. By growing a thin single crystal film (epitaxial layer) on top of the (x = 0.25–0.30) alloy, the silicon lattice expands up to 1.2% which is sufficient to increase the mobility considerably. It has been reported that electron mobility enhancement up to 110% and hole mobility enhancement up to 45% has been achieved in n and p-type MOS transistors.15

9.4. STRUCTURE AND OPERATION OF A MOS TRANSISTOR

The metal-oxide-semiconductor field effect transistor (MOSFET) has been the workhorse of the semiconductor industry. The basic structure is conceptually simple and is the reason why the overwhelming majority of integrated circuits are fabricated with MOS transistors. The active element of a MOS transistor consists of a MOS capacitor, whose operation is briefly described in the next section.

9.4.1. MOS Capacitor

A schematic cross section of a MOS capacitor is shown in Figure 9.15a. The top electrode consists of a conductor that can be a metal such as aluminum or can be doped polysilicon or a silicide. The insulator has traditionally been but could also be oxinitride, or a high-dielectric material. The bottom electrode consists of a semiconductor. It is the semiconductor that makes this MOS capacitor different from a traditional parallel plate capacitor. The corresponding energy band diagram across the metal-oxide-silicon structure is shown in Figure 9.15b. In this diagram the electron energy is positive upwards and the potential is positive downwards. Notice that the Fermi level lies in the bottom

half of the band gap for p-type silicon. The symbol is sometimes called the Fermi potential and is defined as the voltage difference between the intrinsic and the Fermi levels. This voltage can be found from Eqs. (9.8) or (9.9) knowing that

+0.41 V at room temperature.

As can be seen from Figure 9.15b, the band gap of silicon dioxide is much larger (8–9 eV) than that of silicon (1.12 eV) as we would expect from a good insulator. The difference between the vacuum level and the Fermi level is called the work function. The value of silicon workfunction can be found from Figure 9.15b and written as,

in which the quantity is called the electron affinity which corresponds to the energy that an electron at the bottom of the conduction band must acquire to break loose from the

capacitor from a negative value to a positive one. A negative gate voltage will induce an electric field over the insulator that will attract positive charges at the semiconductorinsulator interface. These are the majority carriers, i.e., holes, which will accumulate at the surface. When one makes the voltage slightly positive, the induced electric field will repel the holes from the surface region which results in the creation of a depletion region near the surface, as schematically shown in Figure 9.16. It is convenient to look at the corresponding energy band diagram near the silicon surface. The width of the depletion

The minus sign is for p-type material and the plus sign is for n-type since the ionized acceptors and donors are negative and positive, respectively. One of the important technological parameters of a MOS capacitor and transistor is the threshold voltage The threshold voltage is equal to the gate voltage at the point that strong inversion is reached. We can write the gate voltage using the diagram of Figure 9.16b.

The voltage over the insulator is a function of the charge in the depletion layer and oxide charge The oxide charge is the result of impurities and defects in the insulator. We will assume that is the equivalent charge located at the insulator-silicon interface. These charges are the result of the non-ideality of the oxide and often play a major role in the operation and reliability of MOS devices. The oxide charges can be grouped into mobile charges, oxide-trapped charges, fixed oxide charges and interface-trapped charges. High quality layers should have a defect charge density in the range of or less. At the onset of inversion the surface potential is equal to This allows us to write the threshold voltage as follows,

in which is the work function difference between the gate and substrate material, is called the flat band voltage. Control over the threshold voltage will be very important to ensure proper operation. Notice that the threshold voltage is a function of the doping level through the charge in the depletion region and, to a lesser extent, through the Fermi potential Also, the gate material plays a role through the workfunction Typical gate materials used are highly doped n-type and p-type polysilicon in NMOS and PMOS devices, respectively. The threshold voltage can be adjusted by ion implantation near the silicon-oxide interface. This can be modeled by adding a term, in the expression for the threshold voltage. Applying a gate voltage larger than the threshold voltage will result in a build up of minority carriers at the surface. The charge in the inversion layer per unit area can then be written as,

9.4.2. MOS Transistor

The metal-oxide-semiconductor field-effect transistor consists of a MOS capacitor as described above and two adjacent diodes called source and drain. The structure is schematically shown in Figure 9.17. It has four terminals: the gate, source, drain and substrate terminal. The region underneath the MOS gate is called the channel of the transistor.

9.4.2.1. Long Channel Transistor and I–V Characteristics in Strong Inversion As we discussed in the previous section, the voltage applied to the gate terminal of a MOS

If we continue our experiments and keep increasing the drain voltage, the concentration of electrons in the channel region will not be uniform anymore. This can be easily understood as follows. Close to the source region the voltage determines the charges while near the drain region and the voltage determines the amount of charges in the channel. Since the amount of charges near the drain end of the channel will have decreased as compared to those near the source. This will cause the current to level off as a function of the drain voltage as shown in Figure 9.18. Assuming a gradual-channel approximation, a first order model of the current flow can be derived.13, 16 The current in the triode region can be expressed as,

The parameter m is called the body effect coefficient and can be expressed as

The value of m depends on the substrate doping level and the oxide thickness One tries to keep m as close to 1 as possible. Typical values range between 1.1 and 1.5. If we continue to increase the drain voltage, we reach a point where the channel charge is reduced to zero near the drain. The charge along the channel can be expressed as,

in which the voltage V varies from V = 0 V near the source end and near the drain end of the channel. By increasing the drain voltage, the inversion charge near the drain will become equal to zero when We say that the channel is pinched off and the transistor goes into saturation. The current becomes basically independent of the drain voltage in this region as shown in Figure 9.18. By substituting by in Eq. (9.21), we find that the current in saturation is

equal to,

When the gate length L is made small, the effect of the drain voltage will not be negligible anymore. Increasing the drain voltage will increase the depletion layer of the drain and cause a reduction of the effective gate length. Since the current is proportional to the current will increase with This can be modeled by a channel length modulation parameter The expression of the drain current can now be written as,

The above current-voltage expressions are based on first-order models that are only valid for long channel transistors. For small dimension transistors other effects need to be taken into account. The model gets easily complicated whose parameters in many cases are based on fitting of measured transistor characteristics.

When we discussed the threshold voltage of a MOS capacitor we assumed that the substrate was shorted to ground. In the case of a MOS transistor, the substrate and source terminals can be at different potentials. As a result of the voltage between the source and substrate, the voltage over the depletion region during inversion will increase from to This will affect the threshold voltage through the value of the depletion charge

increases,

The threshold voltage is equal to

in which the top signs apply for NMOS and the bottom signs for PMOS transistors. This effect is called the body effect or the substrate bias effect. The coefficient is related to the parameter m defined in Eq. (9.22). Notice that for a NMOS, the threshold voltage will become more positive with and for a PMOS, the threshold voltage becomes more negative for a more negative The larger the body effect coefficient or the substrate doping concentration, the larger the effect of the substrate-source voltage will be. Since the body effect increases the threshold voltage, the smaller the value of the better.

9.4.2.2. Subthreshold Characteristics In the above discussion we have assumed that the drain current is cut-off when the gate voltage is less than or equal to the threshold

voltage However, the transition between on and off state of the transistor is not that abrupt and there is a transition region, called weak inversion, when mobile minority carriers start to build up at the silicon-oxide interface. These mobile electrons (for a NMOS transistor) will give rise to a diffusion current. The concentration of the electrons in weak inversion is exponentially dependent on the surface potential, according to Eq. (9.8). We can also expect that the drain current will be an exponential function of the gate voltage, as long as the transistor is in weak inversion. The expression for the current in weak inversion is,

For a drain-source voltage a few times larger than kT/q, the transistor is in saturation and the current-voltage relation becomes,

The subthreshold slope S is defined as the gate voltage required to change the drain current by one decade. From the above equation we find the slope to be

The subthreshold slope is typically 60 to 100 mV/decade, depending on the value of m. This is an important parameter of a transistor since it is a measure of how easy it is to switch off a transistor. The factor indicates what fraction of the gate voltage is used to control the charge at the silicon-oxide interface. The smaller the slope, the more efficient the gate voltage will be in controlling the current flow. It should be noted that the actual value of the subthreshold slope can be somewhat larger than given by expression (9.30) due to the presence of interface states. The effect of these states can be modeled by a capacitor in parallel with the depletion capacitor

9.5. SCALING OF TRANSISTOR DIMENSIONS

Over the years, transistor dimensions have been scaled down from about 50 micrometer in the early 1960s to nanoscale dimensions in today’s technology. The main driving forces for reducing the dimensions have been increased circuit density per unit chip area, increased speed of operation, and lower cost per function. The result is that systems on a chip (SOC) have become a reality with today’s technology.17 When reducing transistor dimensions one needs to make sure that the characteristics do not change and that reliability does not become a problem. This was accomplished by a set of guidelines called scaling. Scaling refers to reducing both horizontal and vertical dimensions by the same factor. Let us assume that the scaling factor is called Besides scaling the gate length and width, we also need to scale the vertical dimensions such as the oxide thickness and the depletions width To scale we can increase the substrate doping level and/or reduce the voltage. Let us