Модуль debounce_cnt — антидребезговый счетчик

<Описание устройства>

Описание на Verilog

<Код>

module debounce_cnt #(

parameter N=5,

parameter top=20

) (

input clk, btn,

output realized

);

assign realized = rbtn;

reg [N-1:0] rq;

reg rbtn;

always @(posedge clk) begin

rq <= rq + 1;

if (btn != rbtn) begin

rq <= {N{1'b0}};

rbtn <= btn;

end

else if (rq + 1 == top) begin

rbtn <= btn;

rq <= {N{1'b0}};

end

end

endmodule

RTL-схема

<RTL-схема>

Временная диаграмма

<Описание устройства>

Описание на Verilog

<Код>

module pll_cnt (

input clk_50MHz, rst,

output clk_500kHz, clk_5kHz, clk_50Hz, clk_05Hz

);

plllab pll0 (

.refclk(clk_50MHz),

.rst(rst),

.outclk_0(clk_500kHz)

);

plllab pll1 (

.refclk(clk_50MHz),

.rst(rst),

.outclk_0(clk_5kHz)

);

plllab pll2 (

.refclk(clk_50MHz),

.rst(rst),

.outclk_0(clk_50Hz)

);

plllab pll3 (

.refclk(clk_50MHz),

.rst(rst),

.outclk_0(clk_05Hz)

);

endmodule

RTL-схема

<RTL-схема>

Временная диаграмма

<Описание устройства>

Описание на Verilog

<Код>

module wrapper_cnt (

input R, clk_50MHz,

input en, load, rev,

input clk_btn,

input [1:0] addr,

input [3:0] D,

output [6:0] i7sout, d7sout, r7sout, l7sout

);

wire clk_mux;

wire clk_div, clk_div1;

wire realized_btn;

wire clk_500kHz, clk_5kHz, clk_50Hz, clk_05Hz;

debounce_cnt #(.N(10), .top(1000)) u_debounce (

.clk(clk_50MHz),

.btn(clk_btn),

.realized(realized_btn)

);

div_cnt #(.N(25), .top(25000000)) u_div (

.clk(clk_50MHz),

.R(R),

.en(en),

.clkp(clk_div),

.clkp1(clk_div1)

);

pll_cnt u_pll (

.clk_50MHz(clk_50MHz),

.rst(~R),

.clk_500kHz(clk_500kHz),

.clk_5kHz(clk_5kHz),

.clk_50Hz(clk_50Hz),

.clk_05Hz(clk_05Hz)

);

assign clk_mux = addr [1] ? (addr [0] ? clk_05Hz : clk_div1) : (addr [0] ? clk_div : realized_btn);

wire [3:0] q_inc;

inc_cnt #(.N(4)) u_inc (

.clk(clk_mux),

.R(R),

.en(en),

.Q(q_inc)

);

driver7seg u_driver1 (

.bin(q_inc),

.hex(i7sout)

);

wire [3:0] q_dec;

dec_cnt #(.N(4)) u_dec (

.clk(clk_mux),

.R(R),

.en(en),

.Q(q_dec)

);

driver7seg u_driver2 (

.bin(q_dec),

.hex(d7sout)

);

wire [3:0] q_rev;

rev_cnt #(.N(4)) u_rev (

.clk(clk_mux),

.R(R),

.en(en),

.rev(rev),

.Q(q_rev)

);

driver7seg u_driver3 (

.bin(q_rev),

.hex(r7sout)

);

wire [3:0] q_load;

load_rev_cnt #(.N(4)) u_load (

.clk(clk_mux),

.R(R),

.en(en),

.rev(rev),

.load(load),

.D(D),

.Q(q_load)

);

driver7seg u_driver4 (

.bin(q_load),

.hex(l7sout)

);

endmodule

RTL-схема

<RTL-схема>