Модуль driverascii — драйвер для вывода сигналов в формате ascii
module driverascii(
input [3:0] bin,
output [1*8-1:0] ascii
);
reg [1*8-1:0] rascii;
a
lways
@*
case (bin)
4'b0000: rascii = 8'h30;
4'b0001: rascii = 8'h31;
4'b0010: rascii = 8'h32;
4'b0011: rascii = 8'h33;
4'b0100: rascii = 8'h34;
4'b0101: rascii = 8'h35;
4'b0110: rascii = 8'h36;
4'b0111: rascii = 8'h37;
4'b1000: rascii = 8'h38;
4'b1001:
rascii = 8'h39;
4'b1010: rascii = 8'h41;
4'b1011: rascii = 8'h42;
4'b1100: rascii = 8'h43;
4'b1101: rascii = 8'h44;
4'b1110: rascii = 8'h45;
4'b1111: rascii = 8'h46;
endcase
assign ascii = rascii;
endmodule
Модуль mux_2_1 — мультиплексор 2-в-1
module mux_2_1 (
input addr,
input [1:0] X,
output y
);
assign y = addr ? X[1] : X[0];
endmodule
Модуль mux_8_1 — мультиплексор 8-в-1
module mux_8_1 (
input [2:0] addr,
input [7:0] X,
output Y
);
assign Y = addr[2] ?
(addr[1] ?
(addr[0] ? X[7] : X[6])
:
(addr[0] ? X[5] : X[4]))
:
(addr[1] ?
(addr[0] ? X[3] : X[2])
:
(addr[0] ? X[1] : X[0]));
endmodule
Модуль bus_mux_8_1 — шинный мультиплексор 8-в-1
module bux_mux_8_1 #(
parameter N = 8)
(
input [2:0] addr,
input [N-1:0] X0, X1, X2, X3, X4, X5, X6, X7,
output [N-1:0] Y);
assign Y = addr[2] ? (addr[1] ? (addr[0] ? X7 : X6) : (addr[0] ? X5 : X4)) : (addr[1] ? (addr[0] ? X3 : X2)
:(addr[0] ? X1 : X0));
endmodule
Модуль dmx_1_2 — демультиплексор 1-в-2
module dmx_1_2 (
input addr,
input X,
output reg [1:0] Y );
always @(*) case(addr)
1'd0: Y = {1'bz, X};
1'd1: Y = {X, 1'bz};
default : Y = 2'bzz;
endcase
endmodule
Модуль dmx_1_8 — демультиплексор 1-в-8
module dmx_1_8 (
input [2:0] addr,
input X,
output reg [7:0] Y
);
always @(*) case(addr)
3'h0: Y = {7'bzzzzzzz, X};
3'h1: Y = {6'bzzzzzz, X, 1'bz};
3'h2: Y = {5'bzzzzz, X, 2'bzz};
3'h3: Y = {4'bzzzz, X, 3'bzzz};
3'h4: Y = {3'bzzz, X, 4'bzzzz};
3'h5: Y = {2'bzz, X, 5'bzzzzz};
3'h6: Y = {1'bz, X, 6'bzzzzzz};
3'h7: Y = {X, 7'bzzzzzzz};
default : Y = 8'bzzzzzzzz;
endcase
endmodule
Модуль bus_dmx_1_8 — шинный демультиплексор 1-в-8
module bus_dmx_1_8 #(
parameter N=8
)(
input [2:0] addr,
input [N-1:0] X,
output reg [N-1:0] Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7);
always @(*) case (addr)
3'h0: begin
Y0 = X;
Y1 = {N{1'bz}};
Y2 = {N{1'bz}};
Y3 = {N{1'bz}};
Y4 = {N{1'bz}};
Y5 = {N{1'bz}};
Y6 = {N{1'bz}};
Y7 = {N{1'bz}};
end
3'h1: begin
Y0 = {N{1'bz}};
Y1 = X;
Y2 = {N{1'bz}};
Y3 = {N{1'bz}};
Y4 = {N{1'bz}};
Y5 = {N{1'bz}};
Y6 = {N{1'bz}};
Y7 = {N{1'bz}};
end
3'h2: begin
Y0 = {N{1'bz}};
Y1 = {N{1'bz}};
Y2 = X;
Y3 = {N{1'bz}};
Y4 = {N{1'bz}};
Y5 = {N{1'bz}};
Y6 = {N{1'bz}};
Y7 = {N{1'bz}};
end
3'h3: begin
Y0 = {N{1'bz}};
Y1 = {N{1'bz}};
Y2 = {N{1'bz}};
Y3 = X;
Y4 = {N{1'bz}};
Y5 = {N{1'bz}};
Y6 = {N{1'bz}};
Y7 = {N{1'bz}};
end
3'h4: begin
Y0 = {N{1'bz}};
Y1 = {N{1'bz}};
Y2 = {N{1'bz}};
Y3 = {N{1'bz}};
Y4 = X;
Y5 = {N{1'bz}};
Y6 = {N{1'bz}};
Y7 = {N{1'bz}};
end
3'h5: begin
Y0 = {N{1'bz}};
Y1 = {N{1'bz}};
Y2 = {N{1'bz}};
Y3 = {N{1'bz}};
Y4 = {N{1'bz}};
Y5 = X;
Y6 = {N{1'bz}};
Y7 = {N{1'bz}};
end
3'h6: begin
Y0 = {N{1'bz}};
Y1 = {N{1'bz}};
Y2 = {N{1'bz}};
Y3 = {N{1'bz}};
Y4 = {N{1'bz}};
Y5 = {N{1'bz}};
Y6 = X;
Y7 = {N{1'bz}};
end
3'h7: begin
Y0 = {N{1'bz}};
Y1 = {N{1'bz}};
Y2 = {N{1'bz}};
Y3 = {N{1'bz}};
Y4 = {N{1'bz}};
Y5 = {N{1'bz}};
Y6 = {N{1'bz}};
Y7 = X;
end
default : begin
Y0 = {N{1'bz}};
Y1 = {N{1'bz}};
Y2 = {N{1'bz}};
Y3 = {N{1'bz}};
Y4 = {N{1'bz}};
Y5 = {N{1'bz}};
Y6 = {N{1'bz}};
Y7 = {N{1'bz}};
end
endcase
endmodule
