VHDL lection

Запоминающее устройствоство

architecture myRAM of RAM is const NW : integer := 2**N;

type memory is array (NW-1 downto 0) of std_logic_vector (K-1 downto 0); signal M : memory;

function value (arg : in std_logic_vector) return integer is variable tmp : integer := 0;

begin

for i in arg’high downto arg’low loop tmp := tmp * 2;

if arg(i)=‘1’ then tmp := tmp + 1; end if;

end loop; return tmp;

end value;

Запоминающее устройствоство

begin process (CS) begin

if CS=‘0’ and not CS’stable then

if A’stable(tsu_a_cs) and RW=‘0’ and RW’stable(tsu_rw_cs) and DI’stable(tsu_di_cs) then M (value(A)) <= DI after tcs;

elsif A’stable(tsu_cs) and RW=‘1’ and RW’stable(tsu_rw_cs) then DO <= M (value(A)) after t_cs;

else

for I in 0 to (K-1) loop DO(i) <= ‘Z’;

end loop; end if; end if;

end process; end myRAM;