VHDL lection

Одноразрядный сумматор

Сin SUM

S

A

Сout

B

S = Cin ×(A × B + A × B)+ Cin ×(A Å B)

Cout = A × B + Cin ×( A + B)

Одноразрядный сумматор

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity sum is port(

Cin : in STD_LOGIC;

A : in STD_LOGIC;

B : in STD_LOGIC; S : out STD_LOGIC;

Cout : out STD_LOGIC

);

end sum;

Одноразрядный сумматор

architecture sum of sum is begin

S <= (Cin and ((A and B) or ((not A)and (not B)))) or ((not Cin) and (A xor B));

Cout <= (A and B) or (Cin and (A or B));

end sum;

Одноразрядный сумматор

N-разрядный сумматор

N-разрядный сумматор

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity sum_n is generic(

N : integer := 8

);

port(

Cin : in STD_LOGIC;

A : in STD_LOGIC_VECTOR(N-1 downto 0); B : in STD_LOGIC_VECTOR(N-1 downto 0); Cout : out STD_LOGIC;

S : out STD_LOGIC_VECTOR(N-1 downto 0)

); end sum_n;

N-разрядный сумматор

architecture sum_n of sum_n is component sum is

port(

Cin : in STD_LOGIC;

A : in STD_LOGIC;

B : in STD_LOGIC; S : out STD_LOGIC;

Cout : out STD_LOGIC

);

end component sum;

signal C_in : STD_LOGIC_VECTOR(0 to N); signal C_out : STD_LOGIC_VECTOR(0 to N-1); begin

C_in(0) <= Cin;

sums: for i in 0 to N-1 generate

sum: sum port map (C_in(i), A(i), B(i), S(i), C_out(i)); C_in(i+1) <= C_out (i);

end generate;

Cout <= C_out(N-1); end sum_n;

Запоминающее устройствоство

Запоминающее устройствоство

library ieee;

use ieee.std_kogic_1164.all;

entity RAM is

generic (N, K : integer;