General Description
1.7.3.3 External Clock Signal
An external clock from another CMOS-compatible device can drive the
OSC1 input, with the OSC2 pin unconnected, as Figure 1-11 shows.
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EXTERNAL
CMOS CLOCK
Figure 1-11. External
Clock
NOTE: The bus frequency (fOP) is one-half the external frequency (fOSC) while the processor clock cycle is two times the fOSC period.
1.7.4 External Reset Pin (RESET)
A logic 0 on the bidirectional RESET pin forces the MCU to a known startup state. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 5. Resets.
1.7.5 External Interrupt Request Pin (IRQ)
The IRQ pin is an asynchronous external interrupt pin. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See 4.3.2 External Interrupt (IRQ).
1.7.6 Input Capture Pin (TCAP)
The TCAP pin is the input capture pin for the on-chip capture/compare timer. The TCAP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 8. Capture/Compare Timer.
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General Description
Pin Functions
1.7.7 Output Compare Pin (TCMP)
The TCMP pin is the output compare pin for the on-chip capture/compare timer. See Section 8. Capture/Compare Timer.
1.7.8 Port A I/O Pins (PA7–PA0)
These eight I/O lines comprise port A, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under software control of the data direction registers. See 7.3 Port A.
1.7.9 Port B I/O Pins (PB7–PB0)
These eight I/O pins comprise port B, a general-purpose, bidirectional I/O port. The pins are programmable as either inputs or outputs under software control of the data direction registers. Port B pins also can be configured to function as external interrupts. See 7.4 Port B.
1.7.10 Port C I/O Pins (PC7–PC0)
These eight I/O pins comprise port C, a general-purpose, bidirectional
I/O port. The pins are programmable as either inputs or outputs under software control of the data direction registers. PC7 has a high current sink and source capability. See 7.5 Port C.
1.7.11 Port D I/O Pins (PD7 and PD5–PD0)
These seven lines comprise port D, a fixed input port. All special functions that are enabled (SPI and SCI) affect this port. See 7.6 Port D.
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