MC68HSC705C8A
A.8 3.3-Volt High-Speed SPI Timing
Diagram |
Characteristic(2) |
Symbol |
Min |
Max |
Unit |
|
Number(1) |
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Operating frequency |
fOP(S) |
|
|
fOP |
|
|
Master |
dc |
0.5 |
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|
Slave |
fOP(S) |
dc |
2.1 |
MHz |
|
|
Cycle time |
tCYC(M) |
|
|
tCYC |
|
1 |
Master |
2.0 |
— |
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|
Slave |
tCYC(S) |
480 |
— |
ns |
|
|
Enable lead time |
tLead(M) |
Note (3) |
|
|
|
2 |
Master |
— |
ns |
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|
Slave |
tLead(S) |
240 |
— |
|
|
|
Enable lag time |
tLag(M) |
Note(2) |
|
|
|
3 |
Master |
— |
ns |
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|
Slave |
tLag(S) |
720 |
— |
|
|
|
Clock (SCK) high time |
tW(SCKH)M |
|
|
|
|
4 |
Master |
340 |
— |
ns |
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|
Slave |
tW(SCKH)S |
190 |
— |
|
|
|
Clock (SCK) low time |
tW(SCKL)M |
|
|
|
|
5 |
Master |
340 |
— |
ns |
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|
Slave |
tW(SCKL)S |
190 |
— |
|
|
|
Data setup time (inputs) |
tSU(M) |
|
|
|
|
6 |
Master |
100 |
— |
ns |
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|
Slave |
tSU(S) |
100 |
— |
|
|
|
Data hold time (inputs) |
tH(M) |
|
|
|
|
7 |
Master |
100 |
— |
ns |
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|
Slave |
tH(S) |
100 |
— |
|
|
8 |
Access time(4) |
tA |
0 |
120 |
ns |
|
Slave |
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|
9 |
Disable time(5) |
tDIS |
— |
240 |
ns |
|
Slave |
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|
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Data valid time |
|
|
|
|
|
10 |
Master (before capture edge) |
tV(M) |
0.25 |
— |
tCYC(M) |
|
|
Slave (after enable edge)(6) |
tV(S) |
— |
240 |
ns |
Continued
MC68HC705C8A — |
Rev. 3 |
Technical Data |
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MOTOROLA |
MC68HSC705C8A |
207 |
MC68HSC705C8A
Diagram |
Characteristic(2) |
Symbol |
Min |
Max |
Unit |
|||
Number(1) |
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|
|
|
|
|
|
|
||
|
Data hold time (outputs) |
tHO(M) |
|
|
tCYC(M) |
|||
11 |
Master (after capture edge) |
0.25 |
— |
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|
Slave (after enable edge) |
tHO(S) |
0 |
— |
ns |
|||
12 |
Rise time(7) |
tRM |
— |
100 |
ns |
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SPI outputs (SCK, MOSI, MISO) |
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|
SPI inputs (SCK, MOSI, MISO, |
SS) |
|
tRS |
— |
2.0 |
s |
|
13 |
Fall time(8) |
tFM |
— |
100 |
ns |
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SPI outputs (SCK, MOSI, MISO) |
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|
SPI inputs (SCK, MOSI, MISO, |
SS) |
|
tFS |
— |
2.0 |
s |
|
1.Diagram numbers refer to dimensions in Figure 13-8. SPI Master Timing and Figure 13-9. SPI Slave Timing.
2.VDD = 3.3 V ± 10%; VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
3.Signal production depends on software.
4.Time to data active from high-impedance state
5.Hold time to high-impedance state
6.With 200 pF on all SPI pins
7.20% of VDD to 70% of VDD; CL = 200 pF
8.70% of VDD to 20% of VDD; CL = 200 pF
Technical Data |
|
MC68HC705C8A — Rev. 3 |
|
|
|
208 |
MC68HSC705C8A |
MOTOROLA |
MC68HSC705C8A
A.9 Ordering Information
Table A-2 provides ordering information for the MC68HSC705C8A.
Table A-2. MC68HSC705C8A Order Numbers
Package Type |
Temperature Range |
Order Number |
|
|
|
40-pin plastic dual in-line package (PDIP) |
–40° C to +85° C |
MC68HSC705C8AC(1)P(2) |
44-lead plastic-leaded chip carrier (PLCC) |
–40° C to +85° C |
MC68HSC705C8ACFN(3) |
|
|
|
44-lead ceramic-leaded chip carrier (CLCC) |
–40° C to +85° C |
MC68HSC705C8ACFS(4) |
40-pin ceramic DIP (cerdip) |
–40° C to +85° C |
MC68HSC705C8ACS(5) |
44-pin quad flat pack (QFP) |
–40° C to +85° C |
MC68HSC705C8ACFB(6) |
42-pin shrink dual in-line package (SDIP) |
–40° C to +85° C |
MC68HSC705C8ACB(7) |
1.C = Extended temperature range (–40° C to +85° C)
2.P = Plastic dual in-line package (PDIP)
3.FN = Plastic-leaded chip carrier (PLCC)
4.FS = Ceramic-leaded chip carrier (CLCC)
5.S = Windowed ceramic dual in-line package (cerdip)
6.FB = Quad flat pack (QFP)
7.B = Shrink dual in-line package (SDIP)
MC68HC705C8A — |
Rev. 3 |
Technical Data |
|
|
|
MOTOROLA |
MC68HSC705C8A |
209 |
MC68HSC705C8A
Technical Data |
|
MC68HC705C8A — Rev. 3 |
|
|
|
210 |
MC68HSC705C8A |
MOTOROLA |