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Electrical Specifications

5.0-Volt Control Timing

13.9 5.0-Volt Control Timing

	Characteristic(1)	Symbol	Min	Max	Unit
Frequency of operation
Crystal option		fOSC	—	4.2	MHz
External clock option			dc	4.2

Internal operating frequency
Crystal (fOSC 2)		fOP	—	2.1	MHz
External clock (fOSC 2)			dc	2.1
Cycle time (see Figure 13-7)		tCYC	480	—	ns
Crystal oscillator startup time (see Figure 13-7)		tOXOV	—	100	ms
Stop recovery startup time (crystal oscillator)		tILCH	—	100	ms
(see Figure 13-6)


	pulse width (see Figure 13-7)	tRL	8	—	tCYC
RESET
Timer		tRESL	4.0	—	tCYC
Resolution(2)
		tTH, tTL	125	—	ns
Input capture pulse width (see Figure 13-5)
		tTLTL	(3)	—	tCYC
Input capture pulse period (see Figure 13-5)


Interrupt pulse width low (edge-triggered)		tILIH	125	—	ns
(see Figure 4-2. External Interrupt Timing)


Interrupt pulse period		tILIL	(4)	—	tCYC
(see Figure 4-2. External Interrupt Timing)


OSC1 pulse width		tOH, tOL	90	—	ns

1.VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc; TA = TL to TH

2.Since a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution.

3.The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC.

4.The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC.

MC68HC705C8A —	Rev. 3	Technical Data

MOTOROLA	Electrical Specifications	181

Electrical Specifications

13.10 3.3-Volt Control Timing

	Characteristic(1)	Symbol	Min	Max	Unit
Frequency of operation		fOSC	—	2.0
Crystal option					MHz
			dc	2.0
External clock option


Internal operating frequency			—	1.0
Crystal (fOSC 2)		fOP			MHz
			dc	1.0
External clock (fOSC 2)


Cycle time (see Figure 13-7)		tCYC	1000	—	ns
Crystal oscillator startup time (see Figure 13-7)		tOXOV	—	100	ms
Stop recovery startup time (crystal oscillator)		tILCH	—	100	ms
(see Figure 13-6)


	pulse width, excluding power-up
RESET		tRL	8	—	tCYC
(see Figure 13-7)


Timer		tRESL
Resolution(2)			4.0	—	tCYC
Input capture pulse width (see Figure 13-5)		tTH, tTL	250	—	ns
Input capture pulse period (see Figure 13-5)		tTLTL	(3)	—	tCYC

Interrupt pulse width low (edge-triggered)		tILIH	250	—	ns
(see Figure 4-2. External Interrupt Timing)


Interrupt pulse period		tILIL	(4)	—	tCYC
(see Figure 4-2. External Interrupt Timing)


OSC1 pulse width		tOH, tOL	200	—	ns

1.VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc; TA = TL to TH

2.Since a 2-bit prescaler in the timer must count four internal cycles (tCYC), this is the limiting minimum factor in determining the timer resolution.

3.The minimum period, tTLTL, should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 tCYC.

4.The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC.

EXTERNAL SIGNAL

tTLTL*

tTH*

tTL*

(TCAP PIN 37)

*Refer to timer resolution data in Figure 13-6 and Figure 13-7.

Figure 13-5. Timer Relationships

Technical Data

MC68HC705C8A — Rev. 3

182

Electrical Specifications

MOTOROLA

Electrical Specifications

3.3-Volt Control Timing

OSC1(1)

tRL

RESET

(2)

IRQ

ILIH

(3)

tILCH

4064 tCYC

IRQ

INTERNAL

CLOCK

INTERNAL					1FFF(4)
ADDRESS	1FFE	1FFE	1FFE	1FFE	1FFF(4)

BUS

RESET OR INTERRUPT

VECTOR FETCH

Notes:

1.Represents the internal gating of the OSC1 pin

2.IRQ pin edge-sensitive option

3.IRQ pin level and edge-sensitive option

4.RESET vector address shown for timing example

Figure 13-6. Stop Recovery Timing Diagram

MC68HC705C8A —	Rev. 3	Technical Data

MOTOROLA	Electrical Specifications	183

184	Technical
	Data

Specifications Electrical

MOTOROLA

3 .Rev — MC68HC705C8A

tVDDR

VDD VDD THRESHOLD (1-2 V TYPICAL)

OSC1*

tOXOV

tCYC

INTERNAL

PROCESSOR

CLOCK

INTERNAL

ADDRESS

1FFE

1FFF

NEW PC

1FFE

1FFF

NEW PC

BUS **

INTERNAL

NEW

DATA

PCH

PCL

PCH

PCL

CODE

BUS ***

tRL

RESET

* * *

*OSC1 line is not meant to represent frequency. It is only used to represent time.

**Internal timing signal and bus information are not available externally.

***The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.

Figure 13-7. Power-On Reset and External Reset Timing Diagram

Specifications Electrical

Electrical Specifications

5.0-Volt Serial Peripheral Interface (SPI) Timing

13.11 5.0-Volt Serial Peripheral Interface (SPI) Timing

Number(1)	Characteristic(2)	Symbol	Min	Max	Unit
	Operating frequency	fOP(M)			fOP
	Master	fOP(M)	dc	0.5	fOP
	Slave	fOP(S)	dc	2.1	MHz
	Cycle time	tCYC(M)			tCYC
1	Master	tCYC(M)	2.0	—	tCYC
	Slave	tCYC(S)	480	—	ns
	Enable lead time	tLead(M)	(3)
2	Master	tLead(M)	(3)	—	ns
	Slave	tLead(S)	240	—
	Enable lag time	tLag(M)
3	Master	tLag(M)	(2)	—	ns
	Slave	tLag(S)	720	—
	Clock (SCK) high time	tW(SCKH)M
4	Master	tW(SCKH)M	340	—	ns
	Slave	tW(SCKH)S	190	—
	Clock (SCK) low time	tW(SCKL)M
5	Master	tW(SCKL)M	340	—	ns
	Slave	tW(SCKL)S	190	—
	Data setup time (inputs)	tSU(M)
6	Master	tSU(M)	100	—	ns
	Slave	tSU(S)	100	—
	Data hold time (inputs)	tH(M)
7	Master	tH(M)	100	—	ns
	Slave	tH(S)	100	—
8	Access time(4)	tA	0	120	ns
8	Slave	tA	0	120	ns
	Slave

9	Disable time(5)	tDIS	—	240	ns
9	Slave	tDIS	—	240	ns
	Slave

	Data valid time
10	Master (before capture edge)	tV(M)	0.25	—	tCYC(M)
	Slave (after enable edge)(6)	tV(S)	—	240	ns

Continued

MC68HC705C8A —	Rev. 3	Technical Data

MOTOROLA	Electrical Specifications	185

Electrical Specifications

Number(1)	Characteristic(2)		Symbol	Min	Max	Unit
	Data hold time (outputs)		tHO(M)			tCYC(M)
11	Master (after capture edge)			0.25	—
	Slave (after enable edge)		tHO(S)	0	—	ns
	Rise time(7)		tR(M)	—	100	ns
12	SPI outputs (SCK, MOSI, MISO)
	SPI inputs (SCK, MOSI, MISO,	SS)	tR(S)	—	2.0	s
13	Fall time(8)		tF(M)	—	100	ns
	SPI outputs (SCK, MOSI, MISO)
	SPI inputs (SCK, MOSI, MISO,	SS)	tF(S)	—	2.0	s

1.Numbers refer to dimensions in Figure 13-8 and Figure 13-9.

2.VDD = 5.0 Vdc ± 10%

3.Signal production depends on software.

4.Time to data active from high-impedance state

5.Hold time to high-impedance state

6.With 200 pF on all SPI pins

7.20% of VDD to 70% of VDD; CL = 200 pF

8.70% of VDD to 20% of VDD; CL = 200 pF

Technical Data		MC68HC705C8A — Rev. 3

186	Electrical Specifications	MOTOROLA

Electrical Specifications

3.3-Volt Serial Peripheral Interface (SPI) Timing

13.12 3.3-Volt Serial Peripheral Interface (SPI) Timing

Number(1)	Characteristic(2)	Symbol	Min	Max	Unit
	Operating frequency	fOP(M)			fOP
	Master	fOP(M)	dc	0.5	fOP
	Slave	fOP(S)	dc	2.1	MHz
	Slave	fOP(S)		2.1	MHz
	Cycle time	tCYC(M)			tCYC
1	Master	tCYC(M)	2.0	—	tCYC
	Slave	tCYC(S)	1	—	ns
	Enable lead time	tLead(M)	(3)
2	Master	tLead(M)	(3)	—	ns
	Slave	tLead(S)	500	—
	Enable lag time	tLag(M)
3	Master	tLag(M)	(2)	—	ns
	Slave	tLag(S)	1500	—
	Clock (SCK) high time	tW(SCKH)M
4	Master	tW(SCKH)M	720	—	ns
	Slave	tW(SCKH)S	400	—
	Clock (SCK) low time	tW(SCKL)M
5	Master	tW(SCKL)M	720	—	ns
	Slave	tW(SCKL)S	400	—
	Data setup time (inputs)	tSU(M)
6	Master	tSU(M)	200	—	ns
	Slave	tSU(S)	200	—
	Data hold time (inputs)	tH(M)
7	Master	tH(M)	200	—	ns
	Slave	tH(S)	200	—
8	Access time(4)	tA	0	250	ns
8	Slave	tA	0	250	ns
	Slave

9	Disable time(5)	tDIS	—	500	ns
9	Slave	tDIS	—	500	ns
	Slave

	Data valid time
10	Master (before capture edge)	tV(M)	0.25	—	tCYC(M)
	Slave (after enable edge)(6)	tV(S)	—	500	ns

Continued

MC68HC705C8A —	Rev. 3	Technical Data

MOTOROLA	Electrical Specifications	187

Electrical Specifications

Number(1)	Characteristic(2)		Symbol	Min	Max	Unit
	Data hold time (outputs)		tHO(M)			tCYC(M)
11	Master (after capture edge)			0.25	—
	Slave (after enable edge)		tHO(S)	0	—	ns
	Rise time(7)		tR(M)	—	200	ns
12	SPI outputs (SCK, MOSI, MISO)
	SPI inputs (SCK, MOSI, MISO,	SS)	tR(S)	—	2.0	s
13	Fall time(8)		tF(M)	—	200	ns
	SPI outputs (SCK, MOSI, MISO)
	SPI inputs (SCK, MOSI, MISO,	SS)	tF(S)	—	2.0	s

1.Numbers refer to dimensions in Figure 13-8 and Figure 13-9.

2.VDD = 3.3 Vdc ± 10%

3.Signal production depends on software.

4.Time to data active from high-impedance state

5.Hold time to high-impedance state

6.With 200 pF on all SPI pins

7.20% of VDD to 70% of VDD; CL = 200 pF

8.70% of VDD to 20% of VDD; CL = 200 pF

Technical Data		MC68HC705C8A — Rev. 3

188	Electrical Specifications	MOTOROLA

Electrical Specifications

3.3-Volt Serial Peripheral Interface (SPI) Timing

SS	SS pin of master held high.
INPUT

		1	12	13	12
SCK (CPOL = 0)	NOTE		5
OUTPUT	NOTE	4
OUTPUT		4
				12	13
SCK (CPOL = 1)	NOTE	5
OUTPUT	NOTE		4
OUTPUT			4
				6	7
MISO		MSB IN	BITS 6–1		LSB IN
INPUT		MSB IN	BITS 6–1		LSB IN
INPUT
	10	11		10	11
MOSI		MASTER MSB OUT	BITS 6–1		MASTER LSB OUT
OUTPUT		MASTER MSB OUT	BITS 6–1		MASTER LSB OUT
OUTPUT
	13				12

Note: This first clock edge is generated internally, but is not seen at the SCK pin.

a) SPI Master Timing (CPHA = 0)

SS	SS pin of master held high.
INPUT

	1	13	12
SCK (CPOL = 0)	5			NOTE
OUTPUT	4			NOTE
	4
		12	13
SCK (CPOL = 1)	5			NOTE
OUTPUT	4			NOTE
	4
			6	7
MISO	MSB IN	BITS 6–1		LSB IN
INPUT	MSB IN	BITS 6–1		LSB IN
10	11	10		11
MOSI	MASTER MSB OUT	BITS 6–1	MASTER LSB OUT
OUTPUT	MASTER MSB OUT	BITS 6–1	MASTER LSB OUT
13				12

Note: This last clock edge is generated internally, but is not seen at the SCK pin.

b) SPI Master Timing (CPHA = 1)

Figure 13-8. SPI Master Timing

MC68HC705C8A —	Rev. 3	Technical Data

MOTOROLA	Electrical Specifications	189

Electrical Specifications

INPUT

SCK (CPOL = 0) (INPUT

SCK (CPOL = 1) INPUT

MISO

INPUT

MOSI

OUTPUT

	1	13	12	3
		115
	4
2
	5
		4
8		12	13	9
SLAVE	MSB OUT	BITS 6–1	SLAVE LSB OUT	NOTE
6	7	10	11
MSB IN		BITS 6–1	LSB IN

Note: Not defined, but normally MSB of character just received

a) SPI Slave Timing (CPHA = 0)

INPUT

SCK (CPOL = 0)

INPUT

SCK (CPOL = 1)

INPUT

MISO	NOTE
OUTPUT

MOSI

INPUT

	1
	5
4
5
	4
10
SLAVE	MSB OUT
6	7

MSB IN

BITS 6–1

12
	3
13	9
	SLAVE LSB OUT
11


BITS 6–1						LSB IN

Note: Not defined, but normally LSB of character previously transmitted

b) SPI Slave Timing (CPHA = 1)

Figure 13-9. SPI Slave Timing

Technical Data		MC68HC705C8A — Rev. 3

190	Electrical Specifications	MOTOROLA

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