Serial Peripheral Interface (SPI)

Multiple-SPI Systems

Example:

LDA #$1C ; MSTR = 1, CPOL = 1, CPHA = 1, ; SPR1 = SPR0 = 0

STA SPCR ; SPI control register

LDA #$4C ; MSTR = 0, SPE = 1, CPOL = 1, CPHA = 1, ; SPR1 = SPR0 = 0

STA SPCR ; SPI control register

11.5 Multiple-SPI Systems

In a multiple-SPI system, all PD4/SCK pins are connected together, all PD3/MOSI pins are connected together, and all PD2/MISO pins are connected together.

Before a transmission, one SPI is configured as master and the rest are configured as slaves. Figure 11-4 is a block diagram showing a single master SPI and three slave SPIs.

Figure 11-4. One Master and Three Slaves Block Diagram

Figure 11-5 is another block diagram with two master/slave SPIs and three slave SPIs.

Serial Peripheral Interface (SPI)

Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram

11.6 Serial Clock Polarity and Phase

To accommodate the different serial communication requirements of peripheral devices, software can change the phase and polarity of the SPI serial clock. The clock polarity bit (CPOL) and the clock phase bit

(CPHA), both in the SPCR, control the timing relationship between the serial clock and the transmitted data. Figure 11-6 shows how the CPOL and CPHA bits affect the clock/data timing.

CAPTURE STROBE

Figure 11-6. SPI Clock/Data Timing