Serial Communications Interface (SCI)

SCI I/O Registers

•Framing Errors — If the data recovery logic does not detect a logic

1 where the stop bit should be in an incoming character, it sets the framing error (FE) bit in the SCSR. The FE bit is set at the same time that the RDRF bit is set.

•Receiver Interrupts — These sources can generate SCI receiver interrupt requests:

–Receive Data Register Full (RDRF) — The RDRF bit in the

SCSR indicates that the receive shift register has transferred a character to the SCDR.

–Receiver Overrun (OR) — The OR bit in the SCSR indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR.

–Idle Input (IDLE) — The IDLE bit in the SCSR indicates that 10 or 11 consecutive logic 1s shifted in from the PD0/RDI pin.

10.6SCI I/O Registers

These I/O registers control and monitor SCI operation:

•SCI data register (SCDR)

•SCI control register 1 (SCCR1)

•SCI control register 2 (SCCR2)

•SCI status register (SCSR)

10.6.1SCI Data Register

The SCI data register (SCDR) shown in Figure 10-5 is the buffer for characters received and for characters transmitted.

Serial Communications Interface (SCI)

10.6.2 SCI Control Register 1

SCI control register 1 (SCCR1) shown in Figure 10-6 has these functions:

•Stores ninth SCI data bit received and ninth SCI data bit transmitted

•Controls SCI character length

•Controls SCI wakeup method

Figure 10-6. SCI Control Register 1 (SCCR1)

R8 — Bit 8 (Received)

When the SCI is receiving 9-bit characters, R8 is the ninth bit of the received character. R8 receives the ninth bit at the same time that the

SCDR receives the other eight bits. Reset has no effect on the R8 bit.

T8 — Bit 8 (Transmitted)

When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the transmitted character. T8 is loaded into the transmit shift register at the same time that SCDR is loaded into the transmit shift register.

Reset has no effect on the T8 bit.

M — Character Length Bit

This read/write bit determines whether SCI characters are eight or nine bits long. The ninth bit can be used as an extra stop bit, as a receiver wakeup signal, or as a mark or space parity bit. Reset has no effect on the M bit.

1 = 9-bit SCI characters

0 = 8-bit SCI characters

Serial Communications Interface (SCI)

SCI I/O Registers

WAKE — Wakeup Bit

This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition of the PD0/RDI pin. Reset has no effect on the WAKE bit.

1 = Address mark wakeup

0 = Idle line wakeup

10.6.3 SCI Control Register 2

SCI control register 2 (SCCR2) shown in Figure 10-7 has these functions:

•Enables the SCI receiver and SCI receiver interrupts

•Enables the SCI transmitter and SCI transmitter interrupts

•Enables SCI receiver idle interrupts

•Enables SCI transmission complete interrupts

•Enables SCI wakeup

•Transmits SCI break characters

Figure 10-7. SCI Control Register 2 (SCCR2)

TIE — Transmit Interrupt Enable Bit

This read/write bit enables SCI interrupt requests when the TDRE bit becomes set. Reset clears the TIE bit.

1 = TDRE interrupt requests enabled

0 = TDRE interrupt requests disabled

Serial Communications Interface (SCI)

TCIE — Transmission Complete Interrupt Enable Bit

This read/write bit enables SCI interrupt requests when the TC bit becomes set. Reset clears the TCIE bit.

1 = TC interrupt requests enabled

0 = TC interrupt requests disabled

RIE — Receive Interrupt Enable Bit

This read/write bit enables SCI interrupt requests when the RDRF bit or the OR bit becomes set. Reset clears the RIE bit.

1 = RDRF interrupt requests enabled

0 = RDRF interrupt requests disabled

ILIE — Idle Line Interrupt Enable Bit

This read/write bit enables SCI interrupt requests when the IDLE bit becomes set. Reset clears the ILIE bit.

1 = IDLE interrupt requests enabled

0 = IDLE interrupt requests disabled

TE — Transmit Enable Bit

Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the

PD1/TDO pin. Reset clears the TE bit. 1 = Transmission enabled

0 = Transmission disabled

RE — Receive Enable Bit

Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. Reset clears the RE bit.

1 = Receiver enabled

0 = Receiver disabled

RWU — Receiver Wakeup Enable Bit

This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears the RWU bit and returns the receiver to normal operation. The WAKE bit in SCCR1 determines whether an