EPROM/OTPROM (PROM)

9.5 Control Registers

This subsection describes the three registers that control memory configuration, PROM security, and IRQ edge or level sensitivity; port B pullups; and non-programmable COP enable/disable.

9.5.1 Option Register

The option register shown in Figure 9-4 is used to select the IRQ sensitivity, enable the PROM security, and select the memory configuration.

RAM0 — Random-Access Memory Control Bit 0

1 = Maps 32 bytes of RAM into page zero starting at address $0030. Addresses from $0020 to $002F are reserved. This bit can be read or written at any time, allowing memory configuration to be changed during program execution.

0 = Provides 48 bytes of PROM at location $0020–$005F.

RAM1 — Random-Access Memory Control Bit 1

1 = Maps 96 bytes of RAM into page one starting at address $0100.

This bit can be read or written at any time, allowing memory configuration to be changed during program execution.

0 = Provides 96 bytes of PROM at location $0100.

EPROM/OTPROM (PROM)

Control Registers

SEC — Security Bit

This bit is implemented as an EPROM cell and is not affected by reset.

1 = Security enabled

0 = Security off; bootloader able to be enabled

IRQ — Interrupt Request Pin Sensitivity Bit

IRQ is set only by reset, but can be cleared by software. This bit can only be written once.

1 = IRQ pin is both negative edgeand level-sensitive. 0 = IRQ pin is negative edge-sensitive only.

Bits 5, 4, and 0 — Not used; always read 0

Bit 2 — Unaffected by reset; reads either 1 or 0

9.5.2 Mask Option Register 1

Mask option register 1 (MOR1) shown in Figure 9-5 is an EPROM register that enables the port B pullup devices. Data from MOR1 is latched on the rising edge of the voltage on the RESET pin.

See 4.3.3 Port B Interrupts.

Figure 9-5. Mask Option Register 1 (MOR1)

PBPU7–PBPU0/COPC — Port B Pullup Enable Bits 7–0

These EPROM bits enable the port B pullup devices.

1 = Port B pullups enabled

0 = Port B pullups disabled

EPROM/OTPROM (PROM)

NOTE: PBPU0/COPC programmed to a 1 enables the port B pullup bit. This bit is also used to clear the non-programmable COP (MC68HC05C4A type). Writing to this bit to clear the COP will not affect the state of the port B pull-up (bit 0). See 5.3.3 Programmable and Non-Programmable COP Watchdog Resets.

When using the MC68HC705C8A in an MC68HC705C8 or

MC68HSC705C8 application, program locations $1FF0 and $1FF1 to $00.

9.5.3 Mask Option Register 2

Mask option register 2 (MOR2) shown in Figure 9-6 is an EPROM register that enables the non-programmable COP watchdog. Data from MOR2 is latched on the rising edge of the voltage on the RESET pin.

See 5.3.3 Programmable and Non-Programmable COP Watchdog Resets.

Figure 9-6. Mask Option Register 2 (MOR2)

NCOPE — Non-Programmable COP Watchdog Enable Bit

This EPROM bit enables the non-programmable COP watchdog.

1 = Non-programmable COP watchdog enabled

0 = Non-programmable COP watchdog disabled