Capture/Compare Timer

Reading TRH returns the current value of the high byte of the counter and causes the low byte to be latched into a buffer, as shown in

Figure 8-8. The buffer value remains fixed even if the high byte is read more than once. Reading TRL reads the transparent low byte buffer and completes the read sequence of the timer registers.

INTERNAL DATA BUS

READ TRH

Figure 8-8. Timer Register Reads

NOTE: To prevent interrupts from occurring between readings of TRH and TRL, set the interrupt mask (I bit) in the condition code register before reading TRH, and clear the mask after reading TRL.

8.4.4 Alternate Timer Registers

The alternate timer registers (ATRH and ATRL) shown in Figure 8-9 contain the current high and low bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL is read. Reading does not affect the timer overflow flag (TOF). Writing to the alternate timer registers has no effect.

Capture/Compare Timer

Timer I/O Registers

= Unimplemented

Figure 8-9. Alternate Timer Registers (ATRH and ATRL)

Reading ATRH returns the current value of the high byte of the counter and causes the low byte to be latched into a buffer, as shown in

Figure 8-10.

INTERNAL DATA BUS

READ ATRH

Figure 8-10. Alternate Timer Register Reads

NOTE: To prevent interrupts from occurring between readings of ATRH and

ATRL, set the interrupt mask (I bit) in the condition code register before reading ATRH, and clear the mask after reading ATRL.

Capture/Compare Timer

8.4.5 Input Capture Registers

When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are latched into the read-only input capture registers (ICRH and ICRL) shown in Figure 8-11. Reading ICRH before reading ICRL inhibits further captures until ICRL is read. Reading ICRL after reading the timer status register clears the input capture flag (ICF).

Writing to the input capture registers has no effect.

= Unimplemented

Figure 8-11. Input Capture Registers (ICRH and ICRL)

NOTE: To prevent interrupts from occurring between readings of ICRH and

ICRL, set the interrupt mask (I bit) in the condition code register before reading ICRH and clear the mask after reading ICRL.

Capture/Compare Timer

Timer I/O Registers

8.4.6 Output Compare Registers

When the value of the 16-bit counter matches the value in the read/write output compare registers (OCRH and OCRL) shown in Figure 8-12, the planned TCMP pin action takes place. Writing to OCRH before writing to

OCRL inhibits timer compares until OCRL is written. Reading or writing to OCRL after reading the timer status register clears the output compare flag (OCF).

Figure 8-12. Output Compare Registers (OCRH and OCRL)

To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use this procedure:

1.Disable interrupts by setting the I bit in the condition code register.

2.Write to OCRH. Compares are now inhibited until OCRL is written.

3.Clear bit OCF by reading the timer status register (TSR).

4.Enable the output compare function by writing to OCRL.

5.Enable interrupts by clearing the I bit in the condition code register.

Capture/Compare Timer