Technical Data — MC68HC705C8A
Section 6. Low-Power Modes
6.1 Contents
6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.3.1 SCI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.2 SPI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3.3 Programmable COP Watchdog in Stop Mode . . . . . . . . . . .71 6.3.4 Non-Programmable COP Watchdog in Stop Mode . . . . . . .73
6.4 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.1 Programmable COP Watchdog in Wait Mode . . . . . . . . . . .75
6.4.2 Non-Programmable COP Watchdog in Wait Mode . . . . . . .75
6.5 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.2 Introduction
This section describes the three low-power modes:
•Stop mode
•Wait mode
•Data-retention mode
6.3 Stop Mode
The STOP instruction places the microcontroller unit (MCU) in its lowest power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing including timer, serial communications interface (SCI), and master mode serial peripheral interface (SPI) operation. See Figure 6-1.
MC68HC705C8A — |
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Technical Data |
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Low-Power Modes |
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Low-Power Modes
STOP |
WAIT |
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT
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NO |
RESET |
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EXTERNAL |
YES |
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INTERRUPT |
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NO |
(IRQ) |
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YES |
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TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT: a. STACK
b. SET I BIT
c. VECTOR TO INTERRUPT ROUTINE
OSCILLATOR ACTIVE
TIMER, SCI, AND SPI
CLOCKS ACTIVE
CPU CLOCKS STOPPED
CLEAR I BIT
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NO |
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RESET |
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YES |
EXTERNAL |
NO |
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INTERRUPT |
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(IRQ) |
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YES |
INTERNAL TIMER |
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YES |
INTERRUPT |
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NO |
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RESTART CPU CLOCK |
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YES |
INTERNAL SCI |
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INTERRUPT |
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1. FETCH RESET VECTOR |
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NO |
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OR |
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2. SERVICE INTERRUPT: |
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a. STACK |
YES |
INTERNAL SPI |
NO |
b. SET I BIT |
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INTERRUPT |
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c. VECTOR TO |
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INTERRUPT ROUTINE |
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Figure 6-1. Stop/Wait Mode Function Flowchart
During stop mode, the I bit in the condition code register (CCR) is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output (I/O) lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or reset.
Technical Data |
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MC68HC705C8A — Rev. 3 |
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70 |
Low-Power Modes |
MOTOROLA |
Low-Power Modes
Stop Mode
6.3.1 SCI During Stop Mode
When the MCU enters stop mode, the baud rate generator stops, halting all SCI activity. If the STOP instruction is executed during a transmitter transfer, that transfer is halted. If a low input to the IRQ pin is used to exit stop mode, the transfer resumes.
If the SCI receiver is receiving data and stop mode is entered, received data sampling stops because the baud rate generator stops, and all subsequent data is lost. Therefore, all SCI transfers should be in the idle state when the STOP instruction is executed.
6.3.2 SPI During Stop Mode
When the MCU enters stop mode, the baud rate generator stops, terminating all master mode SPI operations. If the STOP instruction is executed during an SPI transfer, that transfer halts until the MCU exits stop mode by a low signal on the IRQ pin. If reset is used to exit stop mode, the SPI control and status bits are cleared, and the SPI is disabled.
If the MCU is in slave mode when the STOP instruction is executed, the slave SPI continues to operate and can still accept data and clock information in addition to transmitting its own data back to a master device. At the end of a possible transmission with a slave SPI in stop mode, no flags are set until a low on the IRQ pin wakes up the MCU.
NOTE: Although a slave SPI in stop mode can exchange data with a master SPI, the status bits of a slave SPI are inactive in stop mode.
6.3.3 Programmable COP Watchdog in Stop Mode
The STOP instruction turns off the internal oscillator and suspends the computer operating properly (COP) watchdog counter. If the RESET pin brings the MCU out of stop mode, the reset function clears and disables the COP watchdog.
If the IRQ pin brings the MCU out of stop mode, the COP counter resumes counting from its suspended value after the 4064-tCYC clock stabilization delay. See Figure 6-2.
MC68HC705C8A — |
Rev. 3 |
Technical Data |
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MOTOROLA |
Low-Power Modes |
71 |
Low-Power Modes
NOTE: If the clock monitor is enabled (CME = 1), the STOP instruction causes the clock monitor to time out and reset the MCU.
STOP
CLEAR I BIT IN CCR
TURN OFF INTERNAL OSCILLATOR
SUSPEND COP COUNTER
EXTERNAL YES
RESET?
NO
NO
EXTERNAL
INTERRUPT?
YES
TURN ON INTERNAL OSCILLATOR
END OF |
YES |
STABILIZATION |
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DELAY? |
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NO |
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TURN ON INTERNAL OSCILLATOR
CLEAR COP COUNTER
CLEAR PCOPE BIT IN COPCR
END OF |
YES |
STABILIZATION |
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DELAY? |
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NO |
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TURN ON INTERNAL CLOCK
TURN ON INTERNAL CLOCK RESUME COP WATCHDOG COUNT
1. LOAD PC WITH RESET VECTOR
OR
2.SERVICE INTERRUPT:
a.SAVE CPU REGISTERS ON STACK
b.SET I BIT IN CCR
c.LOAD PC WITH INTERRUPT VECTOR
1. LOAD PC WITH RESET VECTOR OR
2.SERVICE INTERRUPT:
a.SAVE CPU REGISTERS ON STACK
b.SET I BIT IN CCR
c.LOAD PC WITH INTERRUPT VECTOR
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Figure 6-2. Programmable COP Watchdog |
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in Stop Mode (PCOPE = 1) Flowchart |
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Technical Data |
MC68HC705C8A — Rev. 3 |
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72 |
Low-Power Modes |
MOTOROLA |