Interrupts

4.3 Interrupt Sources

These sources can generate interrupts:

•Software instructions (SWI)

•External interrupt pin (IRQ)

•Port B pins

•Serial communications interface (SCI):

–SCI transmit data register empty

–SCI transmission complete

–SCI receive data register full

–SCI receiver overrun

–SCI receiver input idle

•Serial peripheral interface (SPI):

–SPI transmission complete

–SPI mode fault

–SPI overrun

The IRQ pin, port B pins, SCI, and SPI can be masked (disabled) by setting the I bit of the condition code register (CCR). The software interrupt (SWI) instruction is non-maskable.

An interrupt temporarily changes the program sequence to process a particular event. An interrupt does not stop the execution of the instruction in progress but takes effect when the current instruction completes its execution. Interrupt processing automatically saves the central processor unit (CPU) registers on the stack and loads the program counter with a user-defined vector address.

4.3.1 Software Interrupt

The software interrupt instruction (SWI) causes a non-maskable interrupt.

Interrupts

Interrupt Sources

4.3.2 External Interrupt (IRQ)

An interrupt signal on the IRQ pin latches an external interrupt request.

After completing the current instruction, the CPU tests these bits:

•IRQ latch

•I bit in the CCR

Setting the I bit in the CCR disables external interrupts.

If the IRQ latch is set and the I bit is clear, the CPU then begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return-from-interrupt (RTI) instruction, the CPU can recognize the new interrupt request. Figure 4-1 shows the logic for external interrupts.

Figure 4-1 shows an external interrupt functional diagram. Figure 4-2 shows an external interrupt timing diagram for the interrupt line. The timing diagram illustrates two treatments of the interrupt line to the processor.

1.Two single pulses on the interrupt line are spaced far enough apart to be serviced. The minimum time between pulses is a function of the length of the interrupt service.

Once a pulse occurs, the next pulse normally should not occur

until an RTI occurs. This time (tILIL) is obtained by adding 19 instruction cycles to the total number of cycles needed to complete

the service routine (not including the RTI instruction).

2.Many interrupt lines are “wire-ORed” to the IRQ line. If the interrupt line remains low after servicing an interrupt, then the CPU continues to recognize an interrupt.

NOTE: The internal interrupt latch is cleared in the first part of the interrupt service routine. Therefore, a new external interrupt pulse could be latched and serviced as soon as the I bit is cleared.

If the IRQ pin is not in use, connect it to the VDD pin.

Interrupts

Interrupt Sources

4.3.3 Port B Interrupts

When these three conditions are true, a port B pin (PBx) acts as an external interrupt pin:

•The corresponding port B pullup bit (PBPUx) in mask option register 1 (MOR1) is programmed to a logic 1.

•The corresponding port B data direction bit (DDRBx) in data direction register B (DDRB) is a logic 0.

•The clear interrupt mask (CLI) instruction has cleared the I bit in the CCR.

MOR1 is an erasable, programmable read-only memory (EPROM) register that enables the port B pullup device. Data from MOR1 is latched on the rising edge of the voltage on the RESET pin. See 9.5.2 Mask Option Register 1.

Port B external interrupt pins can be falling-edge sensitive only or both falling-edge and low-level sensitive, depending on the state of the IRQ bit in the option register at location $1FDF.

When the IRQ bit is a logic 1, a falling edge or a low level on a port B external interrupt pin latches an external interrupt request. As long as any port B external interrupt pin is low, an external interrupt request is present, and the CPU continues to execute the interrupt service routine.

When the IRQ bit is a logic 0, a falling-edge only on a port B external interrupt pin latches an external interrupt request. A subsequent port B external interrupt request can be latched only after the voltage level of the previous port B external interrupt signal returns to a logic 1 and then falls again to a logic 0.

Figure 4-3 shows the port B input/output (I/O) logic.

Interrupts

VDD

RESET

EXTERNAL INTERRUPT VECTOR FETCH

Figure 4-3. Port B I/O Logic