
- •1. Description
- •2. Features
- •3. Block Diagram
- •4. SFR Mapping
- •5. Pin Configuration
- •6. TS80C52X2 Enhanced Features
- •6.1 X2 Feature
- •6.1.1 Description
- •6.2 Dual Data Pointer Register Ddptr
- •6.3 Timer 2
- •6.3.1 Auto-Reload Mode
- •6.3.2 Programmable Clock-Output
- •6.4 TS80C52X2 Serial I/O Port
- •6.4.1 Framing Error Detection
- •6.4.2 Automatic Address Recognition
- •6.4.3 Given Address
- •6.4.4 Broadcast Address
- •6.4.5 Reset Addresses
- •6.5 Interrupt System
- •6.6 Idle mode
- •6.7 Power-Down Mode
- •6.8 ONCETM Mode (ON Chip Emulation)
- •6.9 Power-Off Flag
- •6.10 Reduced EMI Mode
- •7.1 ROM Structure
- •7.2 ROM Lock System
- •7.2.1 Encryption Array
- •7.2.2 Program Lock Bits
- •7.2.3 Signature bytes
- •7.2.4 Verify Algorithm
- •8.1 EPROM Structure
- •8.2 EPROM Lock System
- •8.2.1 Encryption Array
- •8.2.2 Program Lock Bits
- •8.2.3 Signature bytes
- •8.3 EPROM Programming
- •8.3.1 Set-up modes
- •8.3.2 Definition of terms
- •8.3.3 Programming Algorithm
- •8.3.4 Verify algorithm
- •8.4 EPROM Erasure (Windowed Packages Only)
- •8.4.1 Erasure Characteristics
- •9. Signature Bytes
- •10. Electrical Characteristics
- •10.1 Absolute Maximum Ratings (1)
- •10.2 Power consumption measurement
- •10.3 DC Parameters for Standard Voltage
- •10.4 DC Parameters for Low Voltage
- •10.5 AC Parameters
- •10.5.1 Explanation of the AC Symbols
- •10.5.2 External Program Memory Characteristics
- •10.5.3 External Program Memory Read Cycle
- •10.5.4 External Data Memory Characteristics
- •10.5.5 External Data Memory Write Cycle
- •10.5.6 External Data Memory Read Cycle
- •10.5.7 Serial Port Timing - Shift Register Mode
- •10.5.8 Shift Register Timing Waveforms
- •10.5.9 EPROM Programming and Verification Characteristics
- •10.5.10 EPROM Programming and Verification Waveforms
- •10.5.11 External Clock Drive Characteristics (XTAL1)
- •10.5.12 External Clock Drive Waveforms
- •10.5.13 AC Testing Input/Output Waveforms
- •10.5.14 Float Waveforms
- •10.5.15 Clock Waveforms
- •11. Ordering Information

TS80C32X2
TS87C52X2
TS80C52X2
6.10 Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 17. AUXR Register
AUXR - Auxiliary Register (8Eh)
7 |
6 |
5 |
4 |
3 |
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2 |
1 |
0 |
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- |
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- |
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- |
- |
- |
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- |
- |
AO |
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Bit |
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Bit |
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Description |
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Number |
Mnemonic |
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7 |
- |
Reserved |
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The value read from this bit is indeterminate. Do not set this bit. |
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6 |
- |
Reserved |
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The value read from this bit is indeterminate. Do not set this bit. |
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5 |
- |
Reserved |
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The value read from this bit is indeterminate. Do not set this bit. |
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4 |
- |
Reserved |
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The value read from this bit is indeterminate. Do not set this bit. |
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3 |
- |
Reserved |
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The value read from this bit is indeterminate. Do not set this bit. |
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2 |
- |
Reserved |
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The value read from this bit is indeterminate. Do not set this bit. |
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1 |
- |
Reserved |
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The value read from this bit is indeterminate. Do not set this bit. |
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ALE Output bit |
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0 |
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AO |
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Clear to restore ALE operation during internal fetches. |
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Set to disable ALE operation during internal fetches. |
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Reset Value = XXXX XXX0b
Not bit addressable
32 |
Rev.D - 16 November, 2000 |